【CRC 2008最新书】Design of Cost-Efficient Interconnect Processing Units

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1 Towards Multicores: Technology and Software Complexity 1
1.1 Multicore Architecture, Algorithms and Applications . . . . 1
1.1.1 Trends in Multicore Architectures . . . . . . . . . . . 7
1.1.2 Examples of Multicore architectures . . . . . . . . . . 12
1.2 Complexity in Embedded Software . . . . . . . . . . . . . . 16
1.2.1 Application Layer . . . . . . . . . . . . . . . . . . . . 19
1.2.2 Middleware Layer . . . . . . . . . . . . . . . . . . . . 19
1.2.3 RTOS – Drivers - System Programs . . . . . . . . . . 20
1.2.4 Multicore Programming Paradigms . . . . . . . . . . . 23
1.2.5 Concurrency . . . . . . . . . . . . . . . . . . . . . . . 27
1.2.6 Consistency . . . . . . . . . . . . . . . . . . . . . . . . 29
1.3 Technological Issues in Multicore Architectures . . . . . . . . 30
1.3.1 Deep Submicron Effects . . . . . . . . . . . . . . . . . 30
1.3.2 Power Consumption in CMOS Devices . . . . . . . . . 32
1.3.3 Clock Synchronization . . . . . . . . . . . . . . . . . . 34
1.3.4 Supply Power . . . . . . . . . . . . . . . . . . . . . . . 35
1.3.5 Fundamental Concepts for Efficient SoC Design . . . . 35
2 On-Chip Bus vs. Network-on-Chip 41
2.1 Transition from On-Chip Bus to Network-on-Chip . . . . . . 41
2.2 Popular SoC Buses . . . . . . . . . . . . . . . . . . . . . . . 51
2.2.1 The Peripheral Interconnect Bus . . . . . . . . . . . . 51
2.2.2 The Manchester University Asynchronous Bus . . . . 51
2.2.3 The Palmchip CoreFrame . . . . . . . . . . . . . . . . 52
2.2.4 The Avalon Bus . . . . . . . . . . . . . . . . . . . . . 52
2.2.5 The AMBA Bus . . . . . . . . . . . . . . . . . . . . . 52
2.2.6 The IBM CoreConnect . . . . . . . . . . . . . . . . . . 53
2.2.7 The ST Microelectronics STBus . . . . . . . . . . . . 53
2.2.8 The AMBA AXI . . . . . . . . . . . . . . . . . . . . . 54
2.2.9 Wishbone . . . . . . . . . . . . . . . . . . . . . . . . . 55
2.2.10 The MIPS SoC-It . . . . . . . . . . . . . . . . . . . . . 56
2.2.11 The SONICS Silicon Backplane . . . . . . . . . . . . . 56
2.2.12 The Element Interconnect Bus for the Cell Processor . 56
2.3 Existing NoC Architectures . . . . . . . . . . . . . . . . . . . 57
3 NoC Topology 69
3.1 On-Chip Network Topology . . . . . . . . . . . . . . . . . . 69
3.1.1 Theoretical Metrics for NoC Topologies . . . . . . . . 72
3.2 Multistage Interconnection Networks . . . . . . . . . . . . . 74
3.2.1 Blocking MINs . . . . . . . . . . . . . . . . . . . . . . 76
3.2.2 Permutation and Nonblocking Networks . . . . . . . . 79
3.3 Mesh and Torus . . . . . . . . . . . . . . . . . . . . . . . . . 81
3.4 Chordal Rings . . . . . . . . . . . . . . . . . . . . . . . . . . 83
3.5 Other Constant Degree Topologies . . . . . . . . . . . . . . . 89
3.6 The Spidergon STNoC Topology . . . . . . . . . . . . . . . . 96
3.6.1 The ST Octagon Network Processor Topology . . . . . 96
3.6.2 The Spidergon STNoC Topology . . . . . . . . . . . . 98
3.7 Comparisons based on Topology Metrics . . . . . . . . . . . 100
4 The Spidergon STNoC 103
4.1 Spidergon STNoC Interconnect Processing Unit . . . . . . . 103
4.1.1 The Spidergon Topology Family . . . . . . . . . . . . 108
4.2 Switching Strategy . . . . . . . . . . . . . . . . . . . . . . . . 111
4.3 Communication Layering and Packet Structure . . . . . . . . 113
4.3.1 The Packet Format . . . . . . . . . . . . . . . . . . . . 117
4.4 Routing Algorithms . . . . . . . . . . . . . . . . . . . . . . . 118
4.4.1 Spidergon STNoC Routing Algorithms . . . . . . . . . 120
4.5 Livelock, Starvation, and Deadlock . . . . . . . . . . . . . . . 125
4.5.1 Low-level Deadlock . . . . . . . . . . . . . . . . . . . . 126
4.5.2 Protocol Deadlock . . . . . . . . . . . . . . . . . . . . 132
4.6 Protocol Deadlock Avoidance in Spidergon STNoC . . . . . 138
4.7 Spidergon STNoC Building Blocks . . . . . . . . . . . . . . . 140
4.7.1 The Router . . . . . . . . . . . . . . . . . . . . . . . . 141
4.7.2 Network Interface . . . . . . . . . . . . . . . . . . . . 150
4.7.3 Physical Link . . . . . . . . . . . . . . . . . . . . . . . 158
4.8 Tile-based Architecture . . . . . . . . . . . . . . . . . . . . . 164
5 SoC and NoC Design Methodology and Tools 169
5.1 SoC Design Methodology and Tools . . . . . . . . . . . . . . 169
5.1.1 SoC Modeling and Abstraction Levels . . . . . . . . . 171
5.1.2 Transaction-Level Modeling for System-Level Design . 174
5.1.3 General System-Level Design Methodology . . . . . . 177
5.1.4 System-Level Modeling and Performance Evaluation . 181
5.1.5 Design Space Exploration . . . . . . . . . . . . . . . . 185
5.1.6 System-Level Design Tools . . . . . . . . . . . . . . . 185
5.2 NoC Design Methodology and Tools . . . . . . . . . . . . . . 187
5.2.1 NoC Simulation Tools . . . . . . . . . . . . . . . . . . 188
5.3 The On-Chip Communication Network (OCCN) . . . . . . . 191
5.3.1 The OCCN Methodology . . . . . . . . . . . . . . . . 192
5.3.2 The Protocol Data Unit (PDU) . . . . . . . . . . . . . 195
5.3.3 The MasterPort and SlavePort API . . . . . . . . . . 196
5.3.4 OCCN Channel Design Methodology . . . . . . . . . . 201
5.3.5 Case Study: OCCN Communication Refinement . . . 214
6 Conclusions and Future Work 227
6.1 Enhanced IPU Programmability Portfolio . . . . . . . . . . . 229
6.2 IPU Physical Design . . . . . . . . . . . . . . . . . . . . . . . 231
6.3 IPU Design Tools . . . . . . . . . . . . . . . . . . . . . . . . 232
6.4 IPU Design and Verification Methodology . . . . . . . . . . . 234
References 235