高速电流舵DAC（JSSC论文）

mfxf · 发表于 2009-2-18 21:48:48

有个摘要就好了。

原帖由 ultrawang 于 2008-9-27 15:45 发表

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很不错的一篇DAC论文很多人使用Matlab优化结构都是参考这篇论文的

ght · 发表于 2009-2-19 16:19:24

nesta · 发表于 2009-2-19 16:32:39

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 12, DECEMBER 1998
A 10-b, 500-MSample/s CMOS DAC in 0.6 mm2
Chi-Hung Lin and Klaas Bult
Abstract— A 10-b current steering CMOS digital-to-analog
converter (DAC) is described, with optimized performance for
frequency domain applications. For sampling frequencies up to
200 MSample/s, the spurious free dynamic range (SFDR) is
better than 60 dB for signals from dc to Nyquist. For sampling
frequencies up to 400 MSample/s, the SFDR is better than 55 dB
for signals from dc to Nyquist.
The measured differential nonlinearity and integral nonlinearity
are 0.1 least significant bit (LSB) and 0.2 LSB, respectively.
The circuit is fabricated in a 0.35-m, single-poly, four-metal, 3.3-
V, standard digital CMOS process and occupies 0.6 mm2. When
operating at 500 MSample/s, it dissipates 125 mW from a 3.3-V
power supply. This DAC is optimized for embedded applications
with large amounts of digital circuitry.