PLL Design Tutorial 2007 - Dennis Fischette

gift4jo

Practical Tips for Phase Phase-Locked Loop Design 最新版

深入浅出，帮助你复习所有设计PLL中要注意的问题。没有过多不必要的理论，重点放在常用的Charge Pump PLL。

Title: First Time, Every Time. Practical Advice for Phase-Locked Loop Design Success in a Modern CMOS World
Abstract:
The phase-locked loop (PLL) is an often feared and misunderstood beast. Black-box designs
from IP vendors are integrated on-chip with little understanding of the PLL's sensitivities
to process and digital noise. Inexperienced designers read the latest literature and
try to hit a "home run" with their first PLL. Ignorance of the PLL's internal workings
leads to impossible-to-meet specs and inadequate test features. The result?
Costly silicon spins, hapless debug efforts, and missed product windows.
This presentation provides a practical exploration of real-world PLL design
for clock generation and high-speed IO (e.g. PCI-Express) with emphasis on 45nm
and 65nm designs.
Topics include
- achieving a real physical feel for feedback stability
- common circuit implementations and how they can go horribly wrong
- avoiding late nights in the lab with inexpensive test and debug features
- defining, isolating, and measuring PLL jitter
- creating a tape-out checklist to ensure first-pass success
- subtle design implications of high-speed IO clocks
- real-world failures and successes

nesta

不错的冬冬

meseasky

看一看!1

sjxu007

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fanjx

好东西，谢谢了

hustlinjh

不错的咚咚

hujiaomianhao

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ericgjj

还不错啊，下个看看

mainhand

fm,lfl;af