[请教]ISE中的pad to setup与 clock to pad问题

eefresh

初学FPGA,有以下几个问题请教一下大家：

1. ISE中的pad to setup是否就是Quartus中的Tsu?
而ISE中的clock to pad就是Quartus中的Tco?

2.pad to setup/Tsu的含义是否指：加在FPGA pad上的输入信号的最小setup time要求（时钟沿到来前必须保持稳定的时间）？
而clock to pad/Tco的含义是指：FPGA设计内部最后一级reg到对应输出pad的最大延时要求？

3.系统的最大工作频率Fmax的计算是否考虑了上述Tsu,Tco？
  还是只考虑 clock to setup路径的长度而得出的最大频率（把路径分为pad to setup,pad to pad,clock to pad,clock to setup四种）？

4.对pad to setup/Tsu,clock to pad/Tco的约束在什么情况下需要设置（低速设计中不需设置？）？
  如何设置（取经验值？）？

如获指点，不胜感激，谢谢

zhouandy

期待大牛啊

eefresh

望穿秋水

[ 本帖最后由 eefresh 于 2008-9-7 09:37 编辑 ]

liupardon

搬个凳子坐下，等高手讲讲……

zhouandy

大牛都不在啊

lurkerone

同问，期待解答。。。

jokeshe

这个一般是源同步设计中需要加的...从上一级芯片出来的同步信号,其数据相对时钟边沿的有效时间,在FPGA内部你的数据信号到第一个FF是有时延的...所以需要约束这段路径...

输出到下一级芯片...也是需要考虑数据相对于时钟的边沿的滞后与路径延迟...

FMAX应该是考虑到了SET与 HOLD的.不过你可以去查手册看...

tytu

pad to setup time
The maximum time required for the data to enter the chip, travel through logic and routing, and arrive at the input pin of the first synchronous element (flip-flop, latch, or RAM) where that pin has a setup requirement before a clocking signal. Setting a pad to setup time creates an OFFSET IN BEFORE constraint.
file:///D:/Xilinx91i/doc/usenglish/help/iseguide/mergedProjects/plugin_ce/image/ce_pad_to_setup_time.gif
1. Data
2. OFFSET
3. Active edge defined by PERIOD


clock to pad time
The maximum time required for data at the input of a flip-flop or latch to travel through logic and routing and arrive at the output of the chip before the next clock edge. It includes the clock-to-Q delay of the source flip-flop and the path delay from that flip-flop to the output pad. Setting a clock to pad time creates an OFFSET OUT AFTER constraint.
file:///D:/Xilinx91i/doc/usenglish/help/iseguide/mergedProjects/plugin_ce/image/ce_clock_to_pad_time.gif
1. OFFSET
2. Active Edge Defined by PERIOD