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发表于 2010-6-30 16:06:23
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在CMOS运放设计中,一般是通过提高输出电阻来提高增益。
A:沒錯.
但一个理想的运放,应该是输出电阻越小越好。这怎么解释?
A:所以CMOS設計出來的不是理想OP,他的output impedance very large, it meas the OP does not have driving ability.
If the Op drive the MOS gate, the mos sink very few current, the OP can afford the current.
But if it drives low resistance, the OP can be linear any more.
So if the OP drives low resistance, it need driving circuit like "Class AB" in the output portion, the Class AB have almost near "1" gain, but it can drving out large current with high linearity!!!
Steven |
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