【On-Chip ESD】 Protection for Integrated Circuits

andyjackcao

Chapter 1  INTRODUCTION
1
1.1
A LITTLE HISTORICAL STORY 1
1.2
ESD FAILURE C A IC RELIABILITY PROBLEM
2
1.3
ON-CHIP ESD PROTECTION
- GENERAL REMEDY
4
1.4
CHALLENGES IN ESD PROTECTION DESIGN
6
1.5
SCOPE OF THIS BOOK
7
REFERENCES
9
Chapter 2 ESD TEST MODELS
11
2.1
NATURE OF ESD PHEMONEMA
11
2.2
HBM MODEL
14
2.3
MM MODEL
18
2.4
CDM MODEL
21
2.5
TLP MODEL
24
2.6
OTHER MODELS
27
viii
Contents
2.7
ESD ZAPPIN
2.8
SUMMARY
31
REFERENCES
33
Chapter 3 ESD PROTECTION DEVICE SOLUTIONS
35
3.1
35ON-CHIP ESD PROTECTION MECHANISMS
3.2
DIODE AS ESD PROTECTION ELEMENT
37
3.2.1
Diode Device Physics
37
3.2.2
Diode in ESD Protection Operation
40
Diode Parasitic Modelling
3.2.3
41
3.3
42
BJT AS ESD PROTECTION ELEMENT
BJT Device Physics
3.3.1
42
3.3.2
BJT in ESD Protection Operation
46
3.3.3
BJT Parasitic Modelling
49
3.4
MOSFET AS ESD PROTECTION ELEMENT
51
3.4.1
MOSFET Device Physics
51
3.4.2
ggMOSFET in ESD Protection Operation
54
3.4.3
57
MOSFET ParasiticModelling
SCR AS ESD PROTECTION ELEMENT
59
3.5
SCR Device Physics
593.5.1
SCR in ESD Protection Operation
64
3.5.2
67
3.5.3
SCR Parasitic Modelling
SUMMARY
70
3.6
71
REFERENCES
Chapter 4 ESD PROTECTION CIRCUIT SOLUTIONS
73
INPUT ESD PROTECTION SCHEMES
4.1
74
A Primary-Secondary ESD Protection Network
4.1.1
75
Multiple-Finger  ESD Protection Structure
4.1.2
77
Gate-Coupled MOS ESD Protection Structure
4.1.3
80
BJT ESD Protection Network
4.1.4
85
SCR ESD Protection Network
4.1.5
89
OUTPUT ESD PROTECTION SCHEMES
4.2
90
Dedicated Output ESD Protection Network
4.2.1
95
Self-Protection of Output Stages
4.2.2
95
POWER CLAMPS
4.3
96
NMOSPower Clamp
4.3.1
97
SCR Power Clamp
4.3.2
98
DiodeString Power Clamp
4.3.3
102
Switch as Power Clamp
4.3.4
104
SUMMARY
4.4
Chapter 5 ADVANCED ESD PROTECTION
Mixed-Signal, RF and Whole-Chip ESD Protection
107
1075.1
ESD PROTECTION FOR MIXED-SIGNAL ICs
1085.2
ESD PROTECTION FOR RF ICs
LOW-PARASITIC MULTIPLE-MODE
5.3
SOLUTIONS
113
A Dual-Direction ESD Protection Structure
5.3.1
115
An All-in-One Multiple-Mode ESD Protection
5.3.2
Design
121
WHOLE-CHIP ESD PROTECTION SCHEMES
1265.4
5.4.1
Principles for Full-Chip ESD Protection
127
5.4.2
A Pad + Clamp Scheme
127
A Common ESD Discharge Bus Scheme
5.4.3
129
5.5
NON-PORTABILITY IN ESD PROTECTION
130
5.6 SUMMARY
131
REFERENCES
132
Chapter 6
ESD FAILURE ANALYSIS AND MODELING
135
6.1
135WHY ESD FAILURE ANALYSIS?
6.2
ESD FA TECHNIQUES
136
6.3
SOME ESD FAILURE SIGNATURES
138
6.4
ESD FA CORRELATION
155
6.5
LATENT ESD FAILURE
159
6.6
ESD FAILURE MODELING AND CRITERIA
162
6.7
SUMMARY
165
REFERENCES
167
Chapter 7
LAYOUT AND TECHNOLOGY INFLUENCES
ON ESD PROTECTION CIRCUIT DESIGN
171
.1
LAYOUT vs. ESD PROTECTION
171
.2
REGULAR LAYOUT FOR ESD PROTECTION
172
.3
SPECIAL LAYOUT FOR ESD PROTECTION
183
.4
ADVANCED LAYOUT DESIGN CONCEPTS
193
.5
TECHNOLOGY SCALING vs. ESD
PROTECTION
205
.6
NEW TECHNOLOGY vs. ESD PROTECTION
206
.7
ESD PROTECTION FOR SOI AND SiGe
210
7.8
ESD PROTECTION FOR NANO TECHNOLOGY
215
7.9
SUMMARY
216
REFERENCES
217
Chapter 8 ESD SIMULATION-DESIGN
METHODOLOGIES
219
8.1
ESD PROTECTION DESIGN METHODS:
TRIAL-&-ERROR versus PREDICTIVE
219
8.2
ESD DESIGN-SIMULATION: DEVICE LEVEL
versus CIRCUIT LEVEL
221
8.3
ESD PROTECTION DEVICE MODELING
224
8.4
MIXED-MODE ESD SIMULATION FOR
DESIGN PREDICTION
229
8.5
MIXED-MODE ESD SIMULATION:
CASE STUDY
234
Understanding ESD Simulation Results8.5.1
235
8.5.2
Case 1: NMOS ESD Protection Structures in
2390.8mBiCMOS
8.5.3
Case 2: MOS ESD Protection Circuit in 0.35
246
CMOS
8.5.4
Case 3: Metal Interconnect in ESD Protection
249Design
Case 4: A Dual-Direction ESD  Protection
8.5.5
251
Structure in BiCMOS
ESD PROTECTION DESIGN VERIFICATION
2558.6
256
SUMMARY
8.7
258
REFERENCES
261
Chapter 9 ESD C CIRCUITINTERACTIONS
261
CHIP-LEVEL ESD PROTECTION DESIGN
9.1
CIRCUIT-TO-ESD  INFLUENCES:
9.2
262
PRE-MATURE ESD FAILURES
ESD-TO-CIRCUIT INFLUENCES:
9.3
268
CIRCUIT PERFORMANCE DEGRADATION
280
SUMMARY
9.4
282
REFERENCES
Chapter 10 CONCLUSION REMARKS AND
283
FUTURE WORK
ontents xi
10.1
CONCLUSION REMARKS 283
10.2
FUTURE WORK
285
Appendix A
287
SUMMARY FOR ESD TEST STANDARDS
REFERENCES
291
Appendix B
COMMERCIAL ESD TESTING SYSTEMS 293
Appendix C
ESD PROTECTION CIRCUIT DESIGN
CHECKLIST
295
Index
299

[ 本帖最后由 andyjackcao 于 2008-8-11 20:40 编辑 ]

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part A

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part B

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PART C

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PART D

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part E

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