状态机的经典教材FSM-Based Digital Design Using Verilog HDL

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FSM-Based Digital Design Using Verilog HDL
Peter Minns and Ian Elliott

Preface xi
Acknowledgements xv
1 Introduction to Finite-State Machines and State Diagrams for the Design
of Electronic Circuits and Systems 1
1.1 Introduction 1
1.2 Learning Material 2
1.3 Summary 21
2 Using State Diagrams to Control External Hardware Subsystems 23
2.1 Introduction 23
2.2 Learning Material 23
2.3 Summary 38
3 Synthesizing Hardware from a State Diagram 39
3.1 Introduction to Finite-State Machine Synthesis 39
3.2 Learning Material 40
3.3 Summary 66
4 Synchronous Finite-State Machine Designs 67
4.1 Traditional State Diagram Synthesis Method 67
4.2 Dealing with Unused States 69
4.3 Development of a High/Low Alarm Indicator System 71
4.3.1 Testing the Finite-State Machine using a Test-Bench Module 75
4.4 SimpleWaveform Generator 76
4.4.1 Sampling Frequency and Samples perWaveform 78
4.5 The Dice Game 79
4.5.1 Development of the Equations for the Dice Game 81
4.6 Binary Data Serial Transmitter 83
4.6.1 The RE Counter Block in the Shift Register of Figure 4.15 87
4.7 Development of a Serial Asynchronous Receiver 88
4.7.1 Finite-State Machine Equations 91
4.8 Adding Parity Detection to the Serial Receiver System 92
4.8.1 To Incorporate the Parity 92
4.8.2 D-Type Equations for Figure 4.26 94
4.9 An Asynchronous Serial Transmitter System 95
4.9.1 Equations for the Asynchronous Serial Transmitter 98
4.10 ClockedWatchdog Timer 100
4.10.1 D Flip-Flop Equations 102
4.10.2 Output Equation 102
4.11 Summary 103
5 The One Hot Technique in Finite-State Machine Design 105
5.1 The One Hot Technique 105
5.2 A Data Acquisition System 110
5.3 A Shared Memory System 114
5.4 FastWaveform Synthesizer 116
5.4.1 Specification 117
5.4.2 A Possible Solution 118
5.4.3 Equations for the d Inputs to D Flip-Flops 119
5.4.4 Output Equations 120
5.5 Controlling the Finite-State Machine from a Microprocessor/Microcontroller 120
5.6 A Memory-Chip Tester 123
5.7 Comparing One Hot with the more Conventional Design
Method of Chapter 4 126
5.8 A Dynamic Memory Access Controller 127
5.8.1 Flip-Flop Equations 131
5.8.2 Output Equations 131
5.9 How to Control the Dynamic Memory Access from a Microprocessor 132
5.10 Detecting Sequential Binary Sequences using a Finite-State Machine 134
5.11 Summary 143
6 Introduction to Verilog HDL 145
6.1 A Brief Background to Hardware Description Languages 145
6.2 Hardware Modelling with Verilog HDL: the Module 147
6.3 Modules within Modules: Creating Hierarchy 152
6.4 Verilog HDL Simulation: a Complete Example 155
References 162
7 Elements of Verilog HDL 163
7.1 Built-In Primitives and Types 163
ii Contents
7.1.1 Verilog Types 163
7.1.2 Verilog Logic and Numeric Values 167
7.1.3 Specifying Values 169
7.1.4 Verilog HDL Primitive Gates 170
7.2 Operators and Expressions 172
7.3 Example Illustrating the Use of Verilog HDL Operators:
Hamming Code Encoder 185
7.3.1 Simulating the Hamming Encoder 188
References 195
8 Describing Combinational and Sequential Logic using Verilog HDL 197
8.1 The Data-Flow Style of Description: Review of the Continuous Assignment 197
8.2 The Behavioural Style of Description: the Sequential Block 198
8.3 Assignments within Sequential Blocks: Blocking and Nonblocking 204
8.3.1 Sequential Statements 204
8.4 Describing Combinational Logic using a Sequential Block 209
8.5 Describing Sequential Logic using a Sequential Block 217
8.6 Describing Memories 229
8.7 Describing Finite-State Machines 240
8.7.1 Example 1: Chess Clock Controller Finite-State Machine 245
8.7.2 Example 2: Combination Lock Finite-State Machine with
Automatic Lock Feature 252
References 265
9 Asynchronous Finite-State Machines 267
9.1 Introduction 267
9.2 Development of Event-Driven Logic 269
9.3 Using the Sequential Equation to Synthesize an Event Finite-State Machine 272
9.3.1 Short-cut Rule 275
9.4 Implementing the Design using Sum of Product as used
in a Programmable Logic Device 276
9.4.1 Dropping the Present State n and Next State n þ 1 Notation 277
9.5 Development of an Event Version of the Single-Pulse Generator with
Memory Finite-State Machine 277
9.6 Another Event Finite-State Machine Design from Specification
through to Simulation 280
9.6.1 Important Note! 280
9.6.2 A Motor Controller with Fault Current Monitoring 281
9.7 The Hover Mower Finite-State Machine 285
9.7.1 The Specification and a Possible Solution 285
9.8 An Example with a Transition without any Input 289
9.9 Unusual Example: Responding to a Microprocessor-Addressed Location 291
9.10 An Example that uses a Mealy Output 293
9.10.1 TankWater Level Control System with Solutions 293
9.11 An Example using a Relay Circuit 296
Contents iii
9.12 Race Conditions in an Event Finite-State Machine 299
9.12.1 Race between Primary Inputs 300
9.12.2 Race between Secondary State Variables 300
9.12.3 Race between Primary and Secondary Variables 300
9.13 Wait-State Generator for a Microprocessor System 301
9.14 Development of an Asynchronous Finite-State Machine
for a Clothes Spinner System 304
9.15 Caution when using Two-Way Branches 309
9.16 Summary 312
References 312
10 Introduction to Petri Nets 313
10.1 Introduction to Simple Petri Nets 313
10.2 Simple Sequential Example using a Petri Net 318
10.3 Parallel Petri Nets 319
10.3.1 Another Example of a Parallel Petri Net 323
10.4 Synchronizing Flow in a Parallel Petri Net 324
10.4.1 Enabling and Disabling Arcs 325
10.5 Synchronization of Two Petri Nets using Enabling and Disabling Arcs 326
10.6 Control of a Shared Resource 327
10.7 A Serial Receiver of Binary Data 329
10.7.1 Equations for the First Petri Net 333
10.7.2 Output 333
10.7.3 Equations for the Main Petri Net 333
10.7.4 Outputs 333
10.7.5 The Shift Register 334
10.7.6 Equations for the Shift Register 334
10.7.7 The Divide-by-11 Counter 335
10.7.8 The Data Latch 335
10.8 Summary 336
References 336
Appendix A: Logic Gates and Boolean Algebra Used in the Book 337
A.1 Basic Gate Symbols Used in the Book with Boolean Equations 337
A.2 The Exclusive OR and Exclusive NOR 338
A.3 Laws of Boolean Algebra 338
A.3.1 Basic OR Rules 339
A.3.2 Basic AND Rules 339
A.3.3 Associative and Commutative Laws 340
A.3.4 Distributive Laws 340
A.3.5 Auxiliary Law for Static 1 Hazard Removal 341
A.3.5.1 Proof of Auxiliary Rule 341
A.3.6 Consensus Theorem 342
A.3.7 The Effect of Signal Delay in Logic Gates 343
A.3.8 De Morgan’s Theorem 343
iv Contents
A.4 Examples of Applying the Laws of Boolean Algebra 345
A.4.1 Example: Converting AND–OR to NAND 345
A.4.2 Example: Converting AND–OR to NOR 345
A.4.3 Logical Adjacency Rule 345
A.5 Summary 346
Appendix B: Counting and Shifting Circuit Techniques 347
B.1 Basic Up and Down Synchronous Binary Counter Development 347
B.2 Example for a 4-Bit Synchronous Up-Counter Using T-Type Flip-Flops 349
B.3 Parallel-Loading Counters: Using T Flip-Flops 352
B.4 Using D Flip-Flops to Build Parallel-Loading Counters with Cheap
Programmable Logic Devices 353
B.5 Simple Binary Up-Counter: with Parallel Inputs 354
B.6 Clock Circuit to Drive the Counter (And Finite-State Machines) 355
B.7 Counter Design using Don’t Care States 355
B.8 Shift Registers 357
B.9 Asynchronous Receiver Details of Chapter 4 358
B.9.1 The 11-Bit Shift Registers for the Asynchronous Receiver Module 360
B.9.2 Divide-by-11 Counter 362
B.9.3 Complete Simulation of the Asynchronous Receiver Module
of Chapter 4 364
B.10 Summary 365
Appendix C: Tutorial on the Use of Verilog HDL to Simulate a
Finite-State Machine Design 367
C.1 Introduction 367
C.2 The Single Pulse with Memory Synchronous Finite-State Machine
Design: Using Verilog HDL to Simulate 367
C.2.1 Specification 367
C.2.2 Block Diagram 367
C.2.3 State Diagram 368
C.2.4 Equations from the State Diagram 368
C.2.5 Translation into a Verilog Description 369
C.3 Test-Bench Module and its Purpose 372
C.4 Using SynaptiCAD’s VeriLogger Extreme Simulator 376
C.5 Summary 378
Appendix D: Implementing State Machines using Verilog Behavioural Mode 379
D.1 Introduction 379
D.2 The Single-Pulse/Multiple-Pulse Generator with Memory Finite-State
Machine Revisited 379
D.3 The Memory Tester Finite-State Machine in Section 5.6 383
D.4 Summary

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