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楼主 |
发表于 2008-7-11 21:52:00
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显示全部楼层
module test_encoder(
clk,
a,
b,
qh,
d);
input clk;
input a;
input b;
output d;
output qh;
reg qh1;
reg qh2;
reg qh3;
reg qh4 ;
reg[2:0] t1;
reg[2:0] t2;
reg[2:0] t3;
reg[2:0] t4;
reg[1:0] t5;
reg[1:0] t6;
reg[1:0] t7;
reg[1:0] t8;
reg d1;
reg d2;
reg d3;
reg d4;
[email=always@(posedge]always@(posedge[/email] clk)
begin
if(a)
begin
if(t5<=1)
begin
if(!b)
begin
qh1<=0;
end
else
begin
qh1<=1;
end
t5<=t5+1;
end
end
else
begin
t5<=0;
qh1<=1;
end
end
[email=always@(posedge]always@(posedge[/email] clk)
begin
if(b)
begin
if(t6<=1)
begin
if(a)
begin
qh2<=0;
end
else
begin
qh2<=1;
end
t6<=t6+1;
end
end
else
begin
t6<=0;
qh2<=1;
end
end
[email=always@(posedge]always@(posedge[/email] clk)
begin
if(!a)
begin
if(t7<=1)
begin
if(b)
begin
qh3<=0;
end
else
begin
qh3<=1;
end
t7<=t7+1;
end
end
else
begin
t7<=0;
qh3<=1;
end
end
[email=always@(posedge]always@(posedge[/email] clk)
begin
if(!b)
begin
if(t8<=1)
begin
if(!a)
begin
qh4<=0;
end
else
begin
qh4<=1;
end
t8<=t8+1;
end
end
else
begin
t8<=0;
qh4<=1;
end
end
[email=always@(posedge]always@(posedge[/email] clk)
begin
if(a)
begin
if(t1<=4)
begin
if(t1==4)
begin
d1<=1;
end
else
begin
d1<=0;
end
t1<=t1+1;
end
else
begin
d1<=0;
t1<=t1;
end
end
else
begin
d1<=0;
t1<=0;
end
end
[email=always@(posedge]always@(posedge[/email] clk)
begin
if(b)
begin
if(t2<=4)
begin
if(t2==4)
begin
d2<=1;
end
else
begin
d2<=0;
end
t2<=t2+1;
end
else
begin
d2<=0;
t2<=t2;
end
end
else
begin
d2<=0;
t2<=0;
end
end
[email=always@(posedge]always@(posedge[/email] clk)
begin
if(!a)
begin
if(t3<=4)
begin
if(t3==4)
begin
d3<=1;
end
else
begin
d3<=0;
end
t3<=t3+1;
end
else
begin
d3<=0;
t3<=t3;
end
end
else
begin
d3<=0;
t3<=0;
end
end
[email=always@(posedge]always@(posedge[/email] clk)
begin
if(!b)
begin
if(t4<=4)
begin
if(t4==4)
begin
d4<=1;
end
else
begin
d4<=0;
end
t4<=t4+1;
end
else
begin
d4<=0;
t4<=t4;
end
end
else
begin
d4<=0;
t4<=0;
end
end
assign d=(((d1||d2)||d3)||d4);
assign qh=(((qh1&&qh2)&&qh3)&&qh4);
endmod |
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