[Doctor Graduate, UC Berkeley] Semiconductor Flash Memory Scaling

suk.qi

Semiconductor Flash Memory Scaling
by
Min She
B.S. (University of Science and Technology of China) 1996
M.S. (Johns Hopkins University) 1997
A dissertation submitted in partial satisfaction of the
requirements for the degree of
Doctor of Philosophy
in
Engineering-Electrical Engineering and Computer Sciences
in the
GRADUATE DEVISION
of the
UVIVERSITY OF CALIFORNIA, BERKELEY
Committee in charge:
Professor Tsu-Jae King, Chair
Professor Vivek Subramanian
Professor Timothy Sands

Table of Contents
Chapter1 Introduction………………………………………………………………..….1
1.1 Semiconductor memory comparison……………………………………….1
1.2 Semiconductor flash memory scaling……………………………………...5
1.3 Organization………………………………………………………………10
1.4 Reference………………………………………………………………….12
Chapter 2 Modeling of semiconductor nanocrystal memory…………………………14
2.1 Introduction……………………………………………………………….14
2.2 Device modeling………………………………………………………….16
2.2.1 Write/Erase modeling………………………………………………16
2.2.2 Retention time modeling………………………………………….20
2.3 Results and discussion…………………………………………………….23
2.3.1 Impact of nanocrystal size and tunnel oxide thickness on device
performance………………………………………………………...24
2.3.2 Low barrier tunnel material………………………………………26
2.3.3 Semicondcutor nanocrystal memory as DRAM………………….30
2.4 Conclusion………………………………………………………………33
2.5 Reference………………………………………………………………..34
Chapter 3 Low barrier tunnel dielectrics for flash memory……………………………36
3.1 Introduction………………………………………………………………36
3.2 JVD nitride as a tunnel dielectric in floating gate flash memory………...36
3.2.1 Introduction………………………………………………………37
3.2.2 Hot carrier injection efficiency………………………………….38
3.2.3 Retention and erase………………………………………………39
3.2.4 Device fabrication………………………………………………..42
3.2.5 Device characteristics……………………………………………44
3.2.6 Conclusion……………………………………………………….49
3.3 Improved SONOS flash memory with thermal silicon nitride tunnel
Layer …………………………………………………………………..49
3.3.1 Introduction………………………………………………………...49
3.3.2 Device principle……………………………………………………50
3.3.3 Device fabrication……………………………………………….…52
3.3.4 Results and discussion……………………………………………..53
3.3.5 Conclusion…………………………………………………………55
3.4 Reference………………………………………………………………...56
Chapter 4 High-K material as charge trap/storage layer……………………………...59
4.1 Introduction………………………………………………………………59
4.2 Advantages of using high-k materials……………………………………61
4.3 Theoretical device modeling………………………………………….….64
4.4 HfO2 as charge trap layer in SONOS flash memory………………….….69
4.5 TiO2 as charge trap layer…………………………………………………75
4.6 Conclusions and discussion……………………………………………78
4.7 Reference………………………………………………………………80
Chapter 5 FINFET SONOS flash memory…………………………………………..82
5.1 Introduction …………………………………………………………….82
5.2 Experiment…………………………………………………………… 86
5.3 Device characteristics…………………………………………………...90
5.4 A compact FinFET flash memory array………………………………...99
5.5 Summary……………………………………………………………….110
5.6 Reference………………………………………………………………111
5.7 Appendix: Process flow for FinFET SONOS flash……………………112
Chapter 6 Conclusion………………………………………………………………114
6.1 Summary……………………………………………………….……...114
6.2 Recommendations for future work …………………………………...118
6.3 Reference…………………………………………………………….. 121

[ 本帖最后由 suk.qi 于 2008-7-10 16:35 编辑 ]

fanjx

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liuzhieetop

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zhaoqin

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何况BERKELEY

maletuna

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alanchang

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vividsoft

本帖最后由 suk.qi 于 2008-7-10 16:35 编辑 ]附件: 您所在的用户组无法下载或查看附件

yszhao

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ksksees

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motocser

谢谢楼主，顶格