Asynchronous Circuit Design -- A Tutorial , Jens Sparsø

jiangfire

Asynchronous Circuit Design -- A Tutorial


vi ASYNCHRONOUS CIRCUIT DESIGN
3.3 Building blocks 31
3.4 A simple example 33
3.5 Simple applications of rings 35
3.5.1 Sequential circuits 35
3.5.2 Iterative computations 35
3.6 FOR, IF, and WHILE constructs 36
3.7 A more complex example: GCD 38
3.8 Pointers to additional examples 39
3.8.1 A low-power ¯lter bank 39
3.8.2 An asynchronous microprocessor 39
3.8.3 A ¯ne-grain pipelined vector multiplier 40
3.9 Summary 40
4
Performance 41
4.1 Introduction 41
4.2 A qualitative view of performance 42
4.2.1 Example 1: A FIFO used as a shift register 42
4.2.2 Example 2: A shift register with parallel load 44
4.3 Quantifying performance 47
4.3.1 Latency, throughput and wavelength 47
4.3.2 Cycle time of a ring 49
4.3.3 Example 3: Performance of a 3-stage ring 51
4.3.4 Final remarks 52
4.4 Dependency graph analysis 52
4.4.1 Example 4: Dependency graph for a pipeline 52
4.4.2 Example 5: Dependency graph for a 3-stage ring 54
4.5 Summary 56
5
Handshake circuit implementations 57
5.1 The latch 57
5.2 Fork, join, and merge 58
5.3 Function blocks { The basics 60
5.3.1 Introduction 60
5.3.2 Transparency to handshaking 61
5.3.3 Review of ripple-carry addition 64
5.4 Bundled-data function blocks 65
5.4.1 Using matched delays 65
5.4.2 Delay selection 66
5.5 Dual-rail function blocks 67
5.5.1 Delay insensitive minterm synthesis (DIMS) 67
5.5.2 Null Convention Logic 69
5.5.3 Transistor-level CMOS implementations 70
5.5.4 Martin's adder 71
5.6 Hybrid function blocks 73
5.7 MUX and DEMUX 75
5.8 Mutual exclusion, arbitration and metastability 77
5.8.1 Mutual exclusion 77
5.8.2 Arbitration 79
5.8.3 Probability of metastability 79
5.9 Summary 80
Contents vii
6
Speed-independent control circuits 81
6.1 Introduction 81
6.1.1 Asynchronous sequential circuits 81
6.1.2 Hazards 82
6.1.3 Delay models 83
6.1.4 Fundamental mode and input-output mode 83
6.1.5 Synthesis of fundamental mode circuits 84
6.2 Signal transition graphs 86
6.2.1 Petri nets and STGs 86
6.2.2 Some frequently used STG fragments 88
6.3 The basic synthesis procedure 91
6.3.1 Example 1: a C-element 92
6.3.2 Example 2: a circuit with choice 92
6.3.3 Example 2: Hazards in the simple gate implementation 94
6.4 Implementations using state-holding gates 96
6.4.1 Introduction 96
6.4.2 Excitation regions and quiescent regions 97
6.4.3 Example 2: Using state-holding elements 98
6.4.4 The monotonic cover constraint 98
6.4.5 Circuit topologies using state-holding elements 99
6.5 Initialization 101
6.6 Summary of the synthesis process 101
6.7 Petrify: A tool for synthesizing SI circuits from STGs 102
6.8 Design examples using Petrify 104
6.8.1 Example 2 revisited 104
6.8.2 Control circuit for a 4-phase bundled-data latch 106
6.8.3 Control circuit for a 4-phase bundled-data MUX 109
6.9 Summary 113
7
Advanced 4-phase bundled-data
protocols and circuits
115
7.1 Channels and protocols 115
7.1.1 Channel types 115
7.1.2 Data-validity schemes 116
7.1.3 Discussion 116
7.2 Static type checking 118
7.3 More advanced latch control circuits 119
7.4 Summary 121
8
High-level languages and tools 123
8.1 Introduction 123
8.2 Concurrency and message passing in CSP 124
8.3 Tangram: program examples 126
8.3.1 A 2-place shift register 126
8.3.2 A 2-place (ripple) FIFO 126
8.3.3 GCD using while and if statements 127
8.3.4 GCD using guarded commands 128
8.4 Tangram: syntax-directed compilation 128
8.4.1 The 2-place shift register 129
8.4.2 The 2-place FIFO 130
8.4.3 GCD using guarded repetition 131
viii ASYNCHRONOUS CIRCUIT DESIGN
8.5 Martin's translation process 133
8.6 Using VHDL for asynchronous design 134
8.6.1 Introduction 134
8.6.2 VHDL versus CSP-type languages 135
8.6.3 Channel communication and design °ow 136
8.6.4 The abstract channel package 138
8.6.5 The real channel package 142
8.6.6 Partitioning into control and data 144
8.7 Summary 146
Appendix: The VHDL channel packages 148
A.1 The abstract channel package 148
A.2 The real channel package 150
Epilogue 153
References 155
Index

lue96500

非常感谢

xhui

thank you for sharing

zhangbinsniper@

这本跟书，有没有介绍怎么去进行异步设计的时序分析？

weixbox

thankssssssssss

285940684

thanks

risccpu

Good, thanks.

jamyce

谢谢分享!

yangzhenxi

thanks

feitengyu

Asynchronous Circuit Design 好资料啊