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yilan77 · 发表于 2004-8-16 19:47:27

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下面的这个2.5分频程序是verilog100例中的，看完后有几点不解：
1.为什么引入mid?
2. #delaytime out=~out;有何用？
`timescale 1ns/100ps
module frequency5x2(in,out,rst);
input in,rst;
output out;
reg out;
reg mid;
integer counter;
parameter delaytime=25;
always@(posedge rst )

      begin
      counter=0;
      out=0;
      mid=0;
      end
always@(posedge in)
      begin
         if(counter==4)
            begin
            mid=~mid;
            counter=0;
            end
            else
            counter=counter+1;
         end

  always@(negedge in)
      begin
         if(counter==4)
            begin
            mid=~mid;
            counter=0;
            end
            else
            counter=counter+1;
         end

always@(posedge mid )
      begin
      out=~out;
      #delaytime out=~out;
      end
always@(negedge mid)
      begin
      out=~out;
      #delaytime out=~out;
      end
endmodule