verilog的仿真和综合软件 Icarus Verilog-0.8

pyre · 发表于 2008-5-24 23:38:49

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Icarus verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code writen in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by the ``vvp'' command. For synthesis, the compiler generates netlists in the desired format.
具体介绍见：http://www.icarus.com/eda/verilog/

endyson · 发表于 2009-1-22 22:12:59

thank you very much

endyson · 发表于 2009-1-22 22:14:25

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hhc81000 · 发表于 2009-1-27 12:19:11

感谢ing,收藏中

gogo1211 · 发表于 2009-2-19 20:29:10

很好谢谢了

rodiac · 发表于 2009-4-14 20:35:43

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linyis · 发表于 2009-5-6 11:01:59

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linyis · 发表于 2009-5-6 11:03:04

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linyis · 发表于 2009-5-6 11:08:19

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linyis · 发表于 2009-5-6 11:10:03

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verilog的仿真和综合软件 Icarus Verilog-0.8

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