verilog的仿真和综合软件 Icarus Verilog-0.8

pyre

Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code writen in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by the ``vvp'' command. For synthesis, the compiler generates netlists in the desired format.
具体介绍见：http://www.icarus.com/eda/verilog/

yuanwolf2008

帮顶啊

wyx666

终于找到，不知道能不能帮上忙，

buildgates

感谢ing,收藏中

mudu86

感谢ing,收藏中

北伐

解压怎么还需要part3呢

heningbo

liu 几号

comas

good job ~~~

sea7532

少一个，压缩文件还有一部分没传上来