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发表于 2009-6-12 12:09:12
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for deep submicron process, Lmin<1um, no way to hand calculation without aid of hspice simulation,
one pratical way is to fix the VDS and W/L, run DC sweep with VGS and L, based on the series of plots, you have a rough idea what IDS would be, see CMOS
Circuit Design, Layout, and Simulation
Second Edition
chapter 9 for details |
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