详尽透彻！Finite StateMachine: Datapath Design,Optimization,and Implementation

coland

Finite StateMachine:  Datapath Design,Optimization,and Implementation

ABSTRACT
Finite State Machine Datapath Design, Optimization, and Implementation explores the design space
of combined FSM/Datapath implementations. The lecture starts by examining performance issues
in digital systems such as clock skew and its effect on setup and hold time constraints, and the use
of pipelining for increasing system clock frequency. This is followed by de?nitions for latency and
throughput, with associated resource tradeoffs explored in detail through the use of data?ow graphs
and scheduling tables applied to examples taken from digital signal processing applications. Also,
design issues relating to functionality, interfacing, and performance for different types of memories
commonly found in ASICs and FPGAs such as FIFOs, single-ports, and dual-ports are examined.
Selected design examples are presented in implementation-neutral Verilog code and block diagrams,
with associated design ?les available as downloads for both Altera Quartus and Xilinx Virtex FPGA
platforms. A working knowledge of Verilog, logic synthesis, and basic digital design techniques is
required. This lecture is suitable as a companion to the synthesis lecture titled Introduction to Logic
Synthesis using Verilog HDL.

Table of Contents
Chapter 1 – Calculating Maximum Clock Frequency ....................................1
Chapter 2 – Improving design performance .............................................23
Chapter3–Finite State Machine with Datapath (FSMD) Design ........................35
Chapter 4 – Embedded Memory Usage in Finite State Machine with
Datapath (FSMD) Designs ...............................................83

zakknirvana

asdfasfdasdfasdf

0xffff

好东西
谢谢

raislin

Thanks for sharing.

It's great stuff.

kevinwjs

qqqqqqqqqqqqqqqqqqq

coland

顶一下！

crazyanswer

good book

freelion

非常不错,谢谢楼主了

denap

Thanks for sharing!!

jaco.yang

Good! Thanks!