library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity intram is
port(
clock:in std_logic;
clock_in,clock_outut std_logic;
datafrommem:in integer range 0 to 255;
datatomemut integer range 0 to 255;
address:buffer integer range 0 to 255;
weut std_logic;
correctut std_logic
);
end;
architecture ramcontroller of intram is
signal counter:integer range 0 to 3;
signal data:integer range 0 to 255;
begin
process(clock)
begin
if(rising_edge(clock))then
if(counter=counter'high)then
counter<=0;
else
counter<=counter+1;
end if;
end if;
end process;
process(clock)
begin
if(rising_edge(clock))then
if(counter=0)then
if(address=255)then
address<=0;
else
address<=address+1;
end if;
elsif(counter=1)then
datatomem<=address;
we<='1';
elsif(counter=2)then
we<='0';
elsif(counter=3)then
if(datafrommem=address)then
correct<='1';
else
correct<='0';
end if;
end if;
end if;
end process;
process(counter,clock)
begin
if(falling_edge(clock))then
case counter is
when 2 =>clock_in<='1';
when 3 =>clock_out<='1';
clock_in<='0';
when others =>clock_in<='0';
clock_out<='0';
end case;
end if;
end process;
end ramcontroller;