FPGA上的RESET引脚是不是只是chip的reset？

yinchb

这个RESET只不过是FPGA chip本身的reset引脚，而不能作为user design 的reset引脚使用？并且，如果不用STARTUP block的话，自己的module A（reset，A，B）中的reset信号应该怎样在加电后自动产生由0到1的变化呢？

一声叹息

参考xilinx的《Synthesis and Verification Design Guide》中““Understanding the
Global Signals for Simulation”一节。

jackzhang

我记得在做SPARTN XL时一定要加STARTUP 后来做SPARTN II之后，就一直没使用了。

bravelu

apartan II和spartan IIE似乎都可以将GSR的功能应用到你设计中的reset上，没有去查很多资料，但是实际测出来的情况就是如此。

一声叹息

摘自《Synthesis and Verification Design Guide》
The GSR pin on the STARTUP block or the GSRIN pin on the STARTBUF block drives the
GSR net and connects to each flip-flop’s Preset and Clear pin. When you connect a signal
from a pad to the STARTUP block’s GSR pin, the GSR net is activated. Because the GSR net
is built into the silicon it does not appear in the pre-routed netlist file. When the GSR signal
is asserted High (the default), all flip-flops and latches are set to the state they were in at
the end of configuration. When you simulate the routed design, the gate simulator
translation program correctly models the GSR function.
See Chapter 6, “Verifying Your Design” for more information on STARTUP and
STARTBUF.
Note: The following VHDL and Verilog example shows a STARTUP_VIRTEX instantiation using
both GSR and GTS pins for FPGA Compiler II™, LeonardoSpectrum™ and XST.