Papers：Deep Submicron MOSFETs ！

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Papers：Deep Submicron MOSFETs ！
1。M. Jeng, J. Chung, G. May, P. Ko, C. Hu, "Design Guidelines for Deep-Submicron MOSFETs," Tech. Digest of International Electron Devices Meeting (IEDM),
2。J. Chung, M.C. Jeng, G. May, P.K. Ko, C. Hu, "Hot Electron Currents in Deep Submicron MOSFETs," Tech. Digest of International Electron Devices Meeting (IEDM),
3。M.C. Jeng, P.K. Ko, C. Hu, "A Deep Submicron MOSFET Model for Analog/Digital Circuit Simulations



Dr. Chenming Calvin Hu
      is the TSMC Distinguished Chair Professor of Microelectronics in Electrical Engineering and Computer Sciences at University of California, Berkeley. From 2001 to 2004, he was the Chief Technology Officer of TSMC, world's largest dedicated integrated circuits manufacturing company. He founded Celestry Design Technologies, an IC design software company that was acquired by Cadence Design Systems in 2003. He was the board chairman of the non-profit East Bay Chinese School, Oakland, CA.

In 1997, Dr. Hu received the IEEE Jack A. Morton Award for contributions to MOSFET reliability physics. In 1999, he received the DARPA Most Significant Technological Accomplishment Award for FinFET. FinFET is a promising future MOSFET structure and has allowed several corporations and UC Berkeley to reset the world record of the smallest transistor several times down to 5nm gate length. In 2002, he received the IEEE Solid State Circuits Award for the BSIM transistor model. BSIM is the industry standard for IC simulation and is used in the design of most of the world's ICs with a cumulative value of several hundred billion dollars. He has also received UC Berkeley's highest honor for teaching

[ 本帖最后由 semico_ljj 于 2008-4-18 20:53 编辑 ]

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J.E. Chung, M.C. Jeng, J.E. Moon, P.K. Ko, C. Hu, "Performance and Reliability Design Issues for Deep-Submicron MOSFET's," IEEE Trans. on Electron Devices

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J.E. Moon, T. Garfinkel, J. Chung, M. Wong, P.K. Ko, C. Hu, "A New LDD Structure: Total Overlap with Polysilicon Spacer (TOPS)," IEEE Electron Device Letters

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Invited Paper, C. Hu, "IC Reliability Simulation," Proc. IEEE Custom Integrated Circuits Conf

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S. Parke, J. Moon, P. Nee, J. Huang, C. Hu, P.K. Ko, "Gate-Induced Drain Leakage in LDD and Fully-Overlapped LDD MOSFETs," Symp. on VLSI Technology Digest of Tech

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E. Rosenbaum, R. Moazzami, C. Hu, "Implications of Waveform and Thickness Dependence of SiO2 Breakdown on Accelerated Testing," Proc. of Tech. Papers, International Symp. on VLSI Technology, Systems, and Applications, Taipei, Taiwan

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K.N. Quader, P.K. Ko, C. Hu, P. Fang, J.T. Yue, "Simulations of CMOS Circuit Degradation Due to Hot-Carrier Effects," Reliability Physics Symposium, 30th Annual Proceedings

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J.H. Huang, Z.H. Liu, M.C. Jeng, P.K. Ko, C. Hu, "A Physical Model for MOSFET Output Resistance," Tech. Digest International Electron Devices Meeting

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Z.H. Liu, C. Hu, J-H. Huang, T-Y. Chan, M-C. Jeng, P.K. Ko, Y.C. Cheng, "Threshold Voltage Model for Deep-Submicrometer MOSFET's," IEEE Trans. on Electron Devices, Vol. 40, No. 1, January

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J.H. Huang, Z. H. Liu, M.C. Jeng, P. K. Ko, C. Hu, "A Robust Physical and Predictive Model for Deep-Submicrometer MOS Circuit Simulation," Proc. IEEE Custom Integrated Circuit Conf