FREQUENCY SYNTHESIZER FOR BUILT-IN SELF TESTING OF ANALOG IC

kevinwjs

1 INTRODUCTION..................................................................................................................1
1.1 Background and Motivation ........................................................................................... 2
1.2 Challenges and Requirements......................................................................................... 5
2 SIGNAL GENERATION....................................................................................................... 7
2.1 Signal Generation Techniques ........................................................................................ 7
2.1.1 Direct Digital Synthesizer ...................................................................................... 7
2.1.2 Phase Locked Loop (PLL) Based Synthesizer........................................................ 9
2.1.3 Switched-Capacitor Based Sine Wave Generator ................................................ 10
2.2 Phase Locked Loop Architectures ................................................................................ 11
2.2.1 Integer-N Structure ............................................................................................... 11
2.2.2 Fractional-N Structure .......................................................................................... 13
2.3 Frequency Synthesizer Architecture ............................................................................. 15
3 MODIFIED PLL IN FREQUENCY SYNTHESIZER......................................................... 19
3.1Specifications................................................................................................................19
3.2 PLL Analysis................................................................................................................20
3.2.1 Linear Loop Analysis............................................................................................ 20
3.2.2 Phase Frequency Detector..................................................................................... 24
3.2.3 Charge Pump......................................................................................................... 27
3.2.4 Loop Filter............................................................................................................30
3.2.5 Voltage Controlled Oscillator ............................................................................... 34
3.2.6 Loop Divider......................................................................................................... 39
3.3 Additional Blocks.........................................................................................................43
3.3.1 Frequency Down-Converter.................................................................................. 43
3.3.2 Output Selector ..................................................................................................... 49
4 DESIGN CONSIDERATIONS AND SIMULATED RESULTS ........................................ 50
vii
Page
4.1 Stability Analysis..........................................................................................................50
4.2 PLL Design...................................................................................................................55
4.2.1 Phase Detector ...................................................................................................... 55
4.2.2 Charge Pump......................................................................................................... 59
4.2.3 Voltage Controlled Oscillator ............................................................................... 60
4.3 Frequency Down-Converter Design ............................................................................. 64
4.3.1Mixer.....................................................................................................................64
4.3.2Filter......................................................................................................................66
4.4 Output Selector Design................................................................................................. 66
4.4.1 Fixed Divider ........................................................................................................ 66
4.4.2 2:1 Multiplexer...................................................................................................... 69
4.5 Frequency Synthesizer Simulation ............................................................................... 70
5CONCLUSIONS...................................................................................................................78
REFERENCES.............................................................................................................................

fanjx

好的好的看看看看

bbyan

Thanks~

zying

Thanks

jaseper

good resource thanx!

frzhang1

gei hao, mu gai

easyads

heng hao heng hao

pedro888

thanks for your information..........................
thanks..........................................................

pjing57

thanks!!!

hainihao

好东西，谢谢分享！