ABSTRACT
This dissertation presents several improvements to the standard digital input class-
D amplifier architecture. Three different architectures of class-D amplifier have been
proposed as part of this work, and their theoretical verification is done by system-level
simulations. The output stage in all the proposed architecture is driven by Sigma-Delta
Modulation (SDM). The first consists of a delay-line analog-to-digital converter in the
feedback. The second architecture achieves feedback using continuous-time SDM. The
third structure does not employ feedback but suppresses noise using a three-level output
stage. System-level simulations are carried out using MATLAB and SIMULINK. The
structures are then taken through the schematic design and layout using the CADENCE
design suite. The first design is fabricated through the MOSIS design foundry. The
fabricated device is then tested using a custom made test PCB. The results of the testing
are analyzed, and ideas for future enhancements to the overall topology have been
specified.
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发表于 2008-6-28 17:56:40
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