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全数字频率合成器--深亚微米CMOS
ROBERTBOGDANSTASZEWSKI
Texas Instruments
CONTENTS
PREFACExiii
1INTRODUCTION1
1.1FrequencySynthesis / 1
1.1.1NoiseinOscillators / 2
1.1.2FrequencySynthesisTechniques / 5
1.2FrequencySynthesizerasanIntegralPartofanRFTransceiver / 9
1.2.1Transmitter / 10
1.2.2Receiver / 11
1.2.3TowardDirectTransmitterModulation / 12
1.3FrequencySynthesizersforMobile
Communications / 16
1.3.1Integer-N PLLArchitecture / 17
1.3.2Fractional-N PLLArchitecture / 18
1.3.3TowardanAll-DigitalPLLApproach / 23
1.4ImplementationofanRFSynthesizer / 25
1.4.1CMOSvs.TraditionalRFProcessTechnologies / 25
1.4.2Deep-SubmicronCMOS / 25
1.4.3DigitallyIntensiveApproach / 26
1.4.4SystemIntegration / 27
1.4.5SystemIntegrationChallengesfor
Deep-SubmicronCMOS / 29
2DIGITALLYCONTROLLEDOSCILLATOR30
2.1VaractorinaDeep-SubmicronCMOSProcess / 31
2.2FullyDigitalControlofOscillatingFrequency / 33
2.3 LC Tank / 35
2.4OscillatorCore / 37
2.5Open-LoopNarrowbandDigital-to-FrequencyConversion / 39
2.6ExampleImplementation / 45
2.7Time-DomainMathematicalModelofaDCO / 47
2.8Summary / 51
3NORMALIZEDDCO52
3.1OscillatorTransferFunctionandGain / 52
3.2DCOGainEstimation / 53
3.3DCOGainNormalization / 54
3.4PrincipleofSynchronouslyOptimalDCO
TuningWordRetiming / 55
3.5TimeDitheringofDCOTuningInput / 56
3.5.1OscillatorTuneTimeDitheringPrinciple / 56
3.5.2DirectTimeDitheringofTuningInput / 57
3.5.3UpdateClockDitheringScheme / 59
3.6ImplementationofPVTandAcquisitionDCOBits / 60
3.7ImplementationofTrackingDCOBits / 64
3.7.1High-SpeedDitheringofFractionalVaractors /
3.7.2DynamicElementMatchingofVaractors / 70
3.7.3DCOVaractorRearrangement / 71
3.8Time-DomainModel / 73
3.9Summary / 74
4ALL-DIGITALPHASE-LOCKEDLOOP
4.1Phase-DomainOperation / 77
4.2ReferenceClockRetiming / 79
4.3PhaseDetection / 81
4.3.1DifferenceModeofADPLLOperation / 85
4.3.2Integer-DomainOperation / 86
4.4ModuloArithmeticoftheReferenceandVariablePhases / 86
4.4.1Variable-PhaseAccumulator(PVBlock) / 89
4.5Time-to-DigitalConverter / 91
4.5.1FrequencyReferenceEdgeEstimation / 93
4.6FractionalErrorEstimator / 94
4.6.1Fractional-DivisionRatioCompensation / 96
4.6.2TDCResolutionEffectonEstimated
FrequencyResolution / 97
4.6.3ActiveRemovalofFractionalSpurs
ThroughTDC(Optional) / 98
4.7FrequencyReferenceRetimingbyaDCOClock / 100
4.7.1SenseAmpli?er(R)CBasedFlip-Flo / 102
4.7.2GeneralIdeaofClockRetiming / 103
4.7.3Implementation / 104
4.7.4Time-DeferredCalculationoftheVariable
Phase(Optional) / 107
4.8LoopGainFactor / 109
4.8.1Phase-ErrorDynamicRange / 111
4.9Phase-DomainADPLLArchitecture / 112
4.9.1Close-inSpursDuetoInjectionPulling / 114
4.10PLLFrequencyResponse / 115
4.10.1ConversionBetweenthe s-and
z-Domains / 119
4.11NoiseandErrorSources / 119
4.11.1TDCResolutionEffectonPhaseNoise / 120
4.11.2PhaseNoiseDuetoDCO SD Dithering / 122
4.12TypeIIADPLL / 127
4.12.1PLLFrequencyResponseofa
TypeIILoop / 130
4.13Higher-OrderADPLL / 133
4.13.1PLLStabilityAnalysis / 136
4.14NonlinearDifferentialTermofanADPLL / 139
4.14.1QualityMonitoringofanRFClock / 140
4.15DCOGainEstimationUsingaPLL / 141
4.16GearShiftingofPLLGain / 142
4.16.1AutonomousGear-ShiftingMechanism / 143
4.16.2ExtendedGear-ShiftingSchemewith
Zero-PhaseRestart / 148
4.17EdgeSkippingDitheringScheme(Optional) / 154
4.18Summary / 155
5APPLICATION:ADPLL-BASEDTRANSMITT
5.1DirectFrequencyModulationofaDCO / 157
5.1.1Discrete-TimeFrequencyModulation /
5.1.2HybridofPredictive/ClosedPLLOper
5.1.3EffectofFREF/CKRClockMisalignm
5.2Just-in-TimeDCOGainCalculation / 164
5.3GFSKPulseShapingofTransmitterData / 1
5.3.1InterpolativeFilterOperation / 172
5.4PowerAmpli?er / 175
5.5DigitalAmplitudeModulation / 177
5.5.1DiscretePulse-SlimmingControl / 18
5.5.2RegulationofTransmittingPower / 18
5.5.3TuningWordAdjustment / 182
5.5.4FullyDigitalAmplitudeControl / 183
5.6GoingForward olarTransmitter / 183
5.6.1GenericModulator / 186
5.6.2PolarTXRealization / 187
5.7Summary / 188
6BEHAVIORALMODELINGANDSIMULATION
6.1SimulationMethodology / 190
6.2DigitalBlocks / 191
6.3SupportofDigitalStreamProcessing / 192
6.4RandomNumberGenerator / 192
6.5Time-DomainModelingofDCOPhaseNoise / 192
6.5.1ModelingOscillatorJitter / 192
6.5.2ModelingOscillatorWander / 194
6.5.3ModelingOscillatorFlicker(1/f)Noise / 195
6.5.4ClockEdgeDividerEffects / 200
6.5.5VHDLModelRealizationofaDCO / 201
/ 202
6.5.6SupportofPhysical K
DCO
6.6ModelingMetastabilityinFlip-Flops / 203
6.7SimulationResults / 206
6.7.1Time-DomainSimulations / 206
6.7.2Frequency-DeviationSimulations / 207
6.7.3Phase-DomainSimulationsofTransmitters / 209
6.7.4SynthesizerPhase-NoiseSimulations / 209
6.8Summary / 212
7IMPLEMENTATIONANDEXPERIMENTALRESUL
7.1DSPandItsRFInterfacetoDRP / 213
7.2TransmitterCoreImplementation / 214
7.3ICChip / 216
7.4EvaluationBoard / 218
7.5MeasurementEquipment / 218
7.6GFSKTransmitterPerformance / 219
7.7SynthesizerPerformance / 221
7.8SynthesizerSwitchingTransients / 224
7.9DSP-DrivenModulation / 225
7.10PerformanceSummary / 226
7.11Summary / 227
[ 本帖最后由 dlbasin 于 2008-3-30 20:00 编辑 ] |
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