Sample-and-Hold Circuit__論文

kevinwjs

Low Power, High Performance Sample-and-Hold Circuit__論文
This master thesis describes the design of a track-and-hold (T&H) circuitwith 10bit resolution, 80MS/s and 30MHz bandwidth. It is designed in a0.18μm CMOS process with a supply voltage of 1.8 Volt. The circuit issupposed to work together with a 10bit pipelined analog to digital converter.A switched capacitor topology is used for the T&H circuit and the amplifieris a folded cascode OTA with regulated cascode. The switches used are oftransmission gate type.The thesis presents the design decisions, design phase and the theory neededto understand the design decisions and the considerations in the designphase.The results are based on circuit level SPICE simulations in Cadence withfoundry provided BSIM3 transistor models. They show that the circuit has10bit resolution and 7.6mW power consumption, for the worst-casefrequency of 30MHz. The requirements of the dynamic performance are allfulfilled, most of them with large margins

jjw3310

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fanjx

看看怎么样怎么样

fanjx

太好了太好了

Avalon

smaa

thx a lot

smaa

thx a lot

donnie

thanks

donnie

:victory:

denap

Thanks for sharing!!