A Survey on Continuous-Time ΔΣModulators

kevinwjs

INTRODUCTION
1.1 Motivation…………………………………………………………………….1
1.2 Thesis organization…………………………………………………………...2
2. OVERVIEW OF OVERSAMPLING ΔΣADC
2.1 Sampling and Quantization…………………………………………………...3
2.2 Oversampling and Noise Shaping…………………………………………….4
2.3 Performance Increase and Improvement in the ΔΣmodulators………………8
2.4 The Stability of ΔΣ A/D Converters…………………………………………9
2.5 Comparison Between DT and CT ΔΣ Modulators………………………....10
2.6 Continuous-Time Loop Filter Synthesis……………………………………..11
3. ARCHITECTURES
3.1 Single-Stage CT ΔΣ Modulator Topologies………………………………..14
3.2 Multi-Stage CT ΔΣ Modulator Topologies………………………………...26
4. NON-IDEALITIES AND CORRECTION TECHNIQUES
4.1 Non-Idealities in the DAC (I)---Excess Loop Delay………………………...35
4.2 Non-Idealities in the DAC (II)---Clock Jitter……………………………......42
4.3 Non-Idealities of CT Integrators…………………………………………….62
4.4 Error of the Internal Quantizer………………………………………………71
5. IMPLEMENTATION FO CT ΔΣMODULATORS
5.1 System Architecture Considerations…………………………………….......79
5.2 Circuit Designs and Implementations……………………………………….90
TABLE OF CONTENTS (Continued)
Page
5.3 Implementations…………………………………………………………….95

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