Post layout simulation output value difference from Pre schematic simulation.

gmi2000 · 发表于 2024-8-23 13:16:34

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Post Layout Simulation Output value is diffrent from pre simulation circuit. Could you please anyone guide to resolve this error?
Here I have given VDD DC supply voltage = 2 V

hxzjdbl · 发表于 2024-8-23 14:40:20

LVS PASS了么感觉简单的电路功能有问题有可能是设置问题 PIN的顺序正确么

gmi2000 · 发表于 2024-8-23 14:47:50

hxzjdbl 发表于 2024-8-23 14:40
LVS PASS了么感觉简单的电路功能有问题有可能是设置问题 PIN的顺序正确么

Ya. It passed the LVS, and Calibre pex. ya pins are connected. could you please suggest the what is setting problem?

duanzy · 发表于 2024-8-26 10:59:42

感觉衬底打错了啊。如果黄色的是nwell，那么旁边的衬底也应该有nwell啊

gmi2000 · 发表于 2024-8-26 19:30:33

duanzy 发表于 2024-8-26 10:59
感觉衬底打错了啊。如果黄色的是nwell，那么旁边的衬底也应该有nwell啊

yellow one is P+ implant. after the pmos is detached n+ implant (blue one) is generated. pmos is designed under the nwell (purple). nmos is designed using pwell. then also the post and pre simulation values are same.

[讨论] Post layout simulation output value difference from Pre schematic simulation.

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