[请教]avalon总线接自己写的逻辑

xdzxd

我想在pci上借助avalon总线(不用nois)挂上如下程序,可仿真(modelsim)不出结果,如果挂ram就能成,不知道为什么,是不是那几个外接引脚的问题,应该怎么处理呢,如果那位指点一下,在下谢谢了

module avalontest(
avs_s1_clk,
avs_s1_reset,
avs_s1_chipselect,
avs_s1_write,
avs_s1_byteenable,
avs_s1_address,
avs_s1_writedata,
avs_s1_readdata,
avs_s1_export_dataout1,
avs_s1_export_dataout2,
avs_s1_export_dataout3,
avs_s1_export_dataout4
);
input avs_s1_clk;
input avs_s1_reset;
input avs_s1_chipselect;
input avs_s1_write;
input [3:0] avs_s1_byteenable;
input [3:0] avs_s1_address;
input [31:0] avs_s1_writedata;
output [31:0] avs_s1_readdata;
output [31:0] avs_s1_export_dataout1;
output [31:0] avs_s1_export_dataout2;
output [31:0] avs_s1_export_dataout3;
output [31:0] avs_s1_export_dataout4;
reg [31:0] avs_s1_readdata;
reg [31:0] avs_s1_export_dataout1;
reg [31:0] avs_s1_export_dataout2;
reg [31:0] avs_s1_export_dataout3;
reg [31:0] avs_s1_export_dataout4;
[email=always@(posedge]always@(posedge[/email] avs_s1_clk)
begin
if(avs_s1_reset & avs_s1_chipselect & avs_s1_write)
begin
  case(avs_s1_address)
   4'h0:
    avs_s1_export_dataout1<=avs_s1_writedata;
   4'h4:
    avs_s1_export_dataout2<=avs_s1_writedata;
   4'h8:
    avs_s1_export_dataout3<=avs_s1_writedata;
   4'hc:
    avs_s1_export_dataout4<=avs_s1_writedata;
   default:
   begin
    avs_s1_export_dataout1<=avs_s1_export_dataout1;
    avs_s1_export_dataout2<=avs_s1_export_dataout2;
    avs_s1_export_dataout3<=avs_s1_export_dataout3;
    avs_s1_export_dataout4<=avs_s1_export_dataout4;
   end
  endcase
end
end
[email=always@(posedge]always@(posedge[/email] avs_s1_clk)
begin
if(avs_s1_reset & avs_s1_chipselect & !avs_s1_write)
begin
  case(avs_s1_address)
   4'h0:
    avs_s1_readdata<=avs_s1_export_dataout1;
   4'h4:
    avs_s1_readdata<=avs_s1_export_dataout2;
   4'h8:
    avs_s1_readdata<=avs_s1_export_dataout3;
   4'hc:
    avs_s1_readdata<=avs_s1_export_dataout4;
   default:
   begin
    avs_s1_readdata<=avs_s1_readdata;
   end
  endcase
end
end
endmodule