112G VSR Serdes PHY

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Intellectual property-  112G VSR Serder PHY
Process Technology-  N5
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112G VSR PHY meets the growing high bandwidth and low latency needs of high-performance data center applications. The PHY delivers signal integrity and jitter performance that exceeds the IEEE 80 2.3 and OIF standards electrical specifications . The PHY is small in area, low in power consumption, and high in performance, meeting the needs of chip-to-chip, chip-to-module (copper and optical), and copper backplane interconnects, down to 35dB channel loss.

The PHY supports Pulse-Amplitude Modulation 4-Level (PAM-4) and Non-Return-to-Zero (NRZ) signaling to deliver up to 400G Ethernet. The configurable transmitter and DSP-based receiver with Analog-to-Digital Converter (ADC) enable designers to control and optimize signal integrity and performance. The Continuous Calibration and Adaptation (CCA) algorithm provides a robust performance across voltage and temperature variations. The low jitter PLLs, clock and data recovery circuits provide rob ust timing recovery and better jitter performance, while the embedded Bit Error Rate (BER) tester and internal non-destructive eye monitor provide on-chip testability and visibility into channel performance.

The PHY can perform Auto-Negotiation as defined in the IEEE Std 802.3, Clause 73 , using the inbuilt Auto-Negotiation hardware.
The PHY integrates with the Physical Coding Sublayer (PCS) and Media Access Controller (MAC) layers

Features

Receiver AFE containing CTLE, MFEQ and VGAs, 64x Time Interleaved ADC, 25-tap Digital FFE (16 fixed and 9 floating taps), 1- tap Digital DFE Transmitter 5-tap Digital FFE, Low-Power Voltage Mode DAC-based Driver PLL PLL in common lane supports gap-less operation from 10 GHz to 14 GHz Lane Configurations: x8 Additional Ethernet Functions IEEE 802.3 Clause 73 Auto-Negotiation, IEEE 802.3 Link Training (KR Training), Integrated microcontroller and Firmware Embedded temp

Electrostatic Discharge (ESD)	Data Rates
■ Human Body Model (HBM):    ❑  1 kV on high-speed RX/TX pins    ❑ 2 kV on low-speed pins ■ Charged Device Model (CDM):    4A peak discharge current on high speed RX/TX    pins, 6A peak discharge current on low speed pins	■ 1 Gbps to 112 Gbps

Metal Stack	Process Technology
17M_1X_h_1Xb_v_1Xe_h_1Ya_v_1Yb_h_5Y_vhvhv_2Yy2Yx2R_SHDIMM	TSMC 5-nm FinFET Flip-Chip 130 um pitch

PHY Area	Area per Lane	Junction Temperature
x8: 2420.817um x 1087.072um	x8: 0.328943 mm 2 /lane	Functional Range: -40 to 125°C Performance Range: -20 to 105°C

Power Supply	Power Consumption
■ Digital Core (VPDIG): 0.750 +5%/-5% ■ Analog Core (VP): 0.750 +5%/-5% ■ I/O (VPH, VP_OD): 1.200 V +10%/-3% ■ Analog Core (VP_OD): 1.200 V +10%/-3% SoC Digital Core (VDDCORE): >= VPDIG a	Typical Power tbd mW/lane (20 db channel loss) @ 112 Gbps

a. VDDCORE voltage needs to be defined by the SoC designer. The PHY supports level shifters if VDDCORE is elevated to a
voltage other than VPDIG, thus allowing the PHY hard macros to continue to operate at VPDIG.

Electromigration (EM)	Protocols/Specifications
88KPOH@105°C	IEEE 802.3ck