数字综合版图，cds thru导致lvs不通过

coolwayhu

最近通过写代码的方式生成版图，代码里有一对输入和输出端口逻辑上一直是1和0同步变化（属于巧合），因此软件综合的时候在二者之间加上了cds thru来防止短路然后接在了一起。但是这样综合的结果版图lvs过不了，显示找不到对应的pin。这样的问题有人知道如何解决吗，急求呀

coolwayhu

图片在此

knowworlds

转自cadence forum，原创回答：Andrew Beckett

Problem
The cds_thru device from the "basic" library is used when it is required to join up 2 different pins in a schematic (.e.g to join up a VSSA net to a VSS net). How can an LVS mismatch due to this extra device be resolved?

Solution
The LVS mismatch can be resolved as follows:

=== Assura ===
avCompareRules(
   schematic(
      filterDevice("cds_thru" short("src" "dst"))
   ) ;schematic
) ;avCompareRules

Using the above command, Assura will filter the cds_thru device from the schematic and short the 2 terminals. The net connecting to the 1st terminal specified in the command will be retained. For the above example, it will be the net connecting to the "src" terminal.

For a CDL netlist input, the command would be:

avCompareRules(
   schematic(
      filterDevice( "SH" short("src" "dst"))
   ) ;schematic
) ;avCompareRules

cds_thru is exported to a CDL netlist as a resistor with the model "SH" and resistance 0.1 ohms. Alternatively, the following CDL control command can be used in the CDL netlist:
*.RESI 2000

The above means that resistors with R values of 2000 and below will be automatically shorted.

=== PVS ===
lvs_filter_device R(SH) -short -source

=== Calibre ===
LVS FILTER R(SH) SHORT SOURCE

coolwayhu

knowworlds 发表于 2023-8-4 10:51
转自cadence forum，原创回答：Andrew Beckett

Problem

谢谢！我去看下