有谁熟悉Zve extension啊？

orientview

https://groups.google.com/a/grou ... /Voed0k4EBwAJ?pli=1

[color=rgba(0, 0, 0, 0.87)]We are delighted to announce the start of the public review period for
the following proposed standard extensions to the RISC-V ISA:
Zve32x - 32-bit elements with integer and fixed-point operations only
Zve32f - 32-bit elements with integer, fixed-point, and
single-precision floating-point operations only
Zve64x - 64-bit elements with integer and fixed-point operations only
Zve64f - 64-bit elements with integer, fixed-point, and
single-precision floating-point operations only
Zve64d - 64-bit elements with integer, fixed-point, single-precision,
and double-precision floating-point operations

The Zve* standard extensions provide more limited functionality
intended for embedded and microcontroller applications.

The review period begins today, September 20, and ends on Thursday
November 4, 2021 (inclusive).

These extensions are described in the PDF spec available at:
https://github.com/riscv/riscv-v-spec/releases/download/v1.0/riscv-v-spec-1.0.pdf

which was generated from the source available in the following GitHub repo:
https://github.com/riscv/riscv-v-spec/releases/tag/v1.0

To respond to the public review, please either email comments to the
public isa-dev mailing list or add issues and/or pull requests (PRs)
to the Vector GitHub repo: https://github.com/riscv/riscv-v-spec. We
welcome all input and appreciate your time and effort in helping us by
reviewing the specification.

During the public review period, corrections, comments, and
suggestions, will be gathered for review by the Vector Task Group. Any
minor corrections and/or uncontroversial compatible changes will be
incorporated into the specification. Any remaining issues or proposed
changes will be addressed in the public review summary report. If
there are no issues that require incompatible changes to the public
review specification, the Unprivileged ISA Committee will recommend
the updated specifications be approved and ratified by the RISC-V
Technical Steering Committee and the RISC-V Board of Directors.

Thanks to all the contributors for all their hard work.

Kind Regards,
Stephano
--
Stephano Cetola
Director of Technical Programs
RISC-V International