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LEAF(__reset_vector)
.set noreorder
/* Determine processor */
MFC0( t0, C0_PRId)
li t1, M_PRIdImp | M_PRIdCoID
and t0, t1
li t1, PRID_IMP_4Kec | PRID_COMP_MIPS /*0x019000*/
beq t1, t0, is_4Kec
nop
/* wait for DCU is ok */
li t1, 0x1000;
1:
addiu t1, -1
bne t1, zero, 1b
nop
la t0, av_entry
jalr t0 /*5280 will auto flush cache after reset */
nop
is_4Kec:
/**** linked cached (start address 0x9fc00000)
**** Processor is running code uncached (i.e. 0xbfc00000)
****/
/* set EJ_TDO to 4mA , for ICE help*/
lw t0,0xb801a150 ;
or t0, 0x4;
sw t0, 0xb801a150;
/* Clear watch registers */
MTC0( zero, C0_WatchLo)
MTC0( zero, C0_WatchHi)
/* Disable interrupts and KSU field (power up issue) */
MFC0( k0, C0_Status)
li k1, ~(M_StatusIE | M_StatusKSU)
and k0, k1
MTC0( k0, C0_Status)
1:
li k1, KSEG1BASE
la k0, _reset_handler_le /* Defined in linker script */
or k0, k1 /* Make sure it is uncached */
jr k0
nop
/*cy test */
error:
1:
b 1b
nop
.org 0x200
/* 0xBFC00200 TLB refill, 32 bit task */
/*********************************************************/
1: b 1b /* Stay here */
nop
.org 0x280
/* 0xBFC00280 XTLB refill, 64 bit task */
/*********************************************************/
1: b 1b /* Stay here */
nop
.org 0x300
/* 0xBFC00300 Cache error exception */
/*********************************************************/
1: b 1b /* Stay here */
nop
.org 0x380
/* 0xBFC00380 General exception */
/*********************************************************/
li t1, 0x49;
sw t1, 0xb801b200;
1: /* Stay here */
b 1b
nop
.org 0x400
/* 0xBFC00400 Catch interrupt exceptions, some QEDs only */
/*********************************************************/
1: b 1b /* Stay here */
nop
.org 0x480
/* 0xBFC00480 EJTAG debug exception -- don't touch ANY GPR */
/******************************************************************
* This exception cannot be moved from here, so below code
* transfers it to RAM entry 0x80000300. The RAM entry will look
* similar, which may give this sequence of machine instructions:
* bfc0049c: jr v0
* bfc004a0: mfc0 v0, C0_DESAVE
* (v0): mtc0 xx, CO-DESAVE
* Notes on hazard:
* On CPUs without GPR interlocking, xx must be different from v0.
* The mfc0 and mtc0 placed back to back should not be a problem,
* as the read in CP0 takes place at an earlier stage than write,
* and DESAVE is a scratchpad register with no operational effects.
* Below: Two instructions between mtc0 and mfc0 is sufficient.
*/
mtc0 v0, C0_DESAVE
li v0, KSEG0(SYS_EJTAG_RAM_VECTOR_OFS)
jr v0
mfc0 v0, C0_DESAVE
.org 0x500
/* 0xBFC00500 Vector table for shell functions */
END(__reset_vector) |
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