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module booth4_8(
done,
result,
multiplier,
multiplicand,
start,
clk
);
parameter N=8;
reg [3:0]index_i;
reg [N+1:0]z;
reg [N+1:0]x_c1;
reg [N+1:0]x_c2;
reg [N+1:0]x1;
reg [N+1:0]x2;
reg [N+2:0]y;
reg finished;
reg [1:0]current_state;
reg [1:0]next_state;
output done;
output [N*2+3:0]result;
input [N-1:0]multiplier;
input [N-1:0]multiplicand;
input start;
input clk;
parameter Init=0;
parameter Ready=1;
parameter Acc=2;
parameter Done=3;
assign done=finished;
assign result[N*2+3:0]={z[N+1:0],y[N+2:1]};
always @(posedge clk or negedge start)
if (!start)
current_state<=Init;
else
current_state<=next_state;
always @(posedge clk)
if (current_state==Acc)
index_i<=index_i+1;
else
index_i<=0;
always @(current_state or index_i)
case (current_state)
Init:
begin
finished=0;
end
Ready:
begin
x1={2*multiplier[N-1],multiplier[N-1:0]};
x2={multiplier[N-1],multiplier[N-1:0],1'b0};
x_c1=~{2*multiplier[N-1],multiplier[N-1:0]}+1;
x_c2=~{multiplier[N-1],multiplier[N-1:0],1'b0}+1;
y={2*{multiplicand[N-1]},multiplicand[N-1:0],1'b0};
z=0;
end
Acc:
begin
case (y[2:0])
3'b001 || 3'b010:
begin
z=z+x1;
{z[N+1:0],y[N+2:0]}={2*z[N+1],z[N+1:0],y[N+2:2]};
end
3'b101 || 3'b110:
begin
z=z+x_c1;
{z[N+1:0],y[N+2:0]}={2*z[N+1],z[N+1:0],y[N+2:2]};
end
3'b011:
begin
z=z+x2;
{z[N+1:0],y[N+2:0]}={2*z[N+1],z[N+1:0],y[N+2:2]};
end
3'b100:
begin
z=z+x_c2;
{z[N+1:0],y[N+2:0]}={2*z[N+1],z[N+1:0],y[N+2:2]};
end
default:
begin
{z[N+1:0],y[N+2:0]}={2*z[N+1],z[N+1:0],y[N+2:2]};
end
endcase
end
default:
begin
finished=1;
end
endcase
always @(current_state or index_i)
case (current_state )
Init:
begin
next_state=Ready;
end
Ready:
begin
next_state=Acc;
end
Acc:
begin
if(index_i==4'h5)
begin
next_state=Done;
end
end
endcase
endmodule
`timescale 1 ps/ 1 ps
module test_8_booth4;
reg [7:0] multiplier;
reg [7:0] multiplicand;
reg start;
reg clk;
wire done;
wire [19:0] result;
booth4_8 pangzi (
.done(done),
.result(result),
.multiplier(multiplier),
.multiplicand(multiplicand),
.start(start),
.clk(clk)
);
initial
begin
multiplicand=8'h59;
multiplier=8'h2e;
start = 0;
clk = 0;
#100;
start=1;
#1000;
start=0;
#100;
end
always #10 clk=~clk;
endmodule |
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