今天看了下Doering的Handbook of Semiconductor Manufacturing Technology其中有Integrated-Circuit
Packaging 一章中有一段讲是这么写得： In a parallel vein, wire bonding is more applicable to peripherally bonded chips. With peripheral I/O connections, the voltage drop along the chip’s power and ground lines will impact the signal/noise immunity for medium and high power chips.
不是很理解，请教下是什么意思？为什么在平行方向，引线接合法是最适合的？封装的形式又是怎么影响各个引脚的呢
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发表于 2014-2-8 08:54:47
