[求助]我设计的寄存器组资源占用太大,请帮忙修改一下

zhu1982lin

我实现了一个 16*8bit的寄存器组 有一个输入端, 两个输出端,但是占用了 192个 逻辑单元.使用的是 EP1C6, QuartusII 4.2. 请帮我改一下,使他少占用资源,我是用在 微处理器 上的,要求速度快,且能同时读写,所以不能用 FPGA 内的 M4K 模块.
源代码如下:
library ieee;
  use ieee.std_logic_1164.all;
  use ieee.std_logic_arith.all;
  use ieee.std_logic_unsigned.all;
entity REGS is
  generic (
    WIDTH         : in  natural := 8
  );
  port (
CLK           : in  std_logic;
DIN           : in  std_logic_vector(WIDTH-1 downto 0);
DIN_ADDR      : in  std_logic_vector(3 downto 0);
WEN           : in  std_logic;
DOUT0         : out std_logic_vector(WIDTH-1 downto 0);
DOUT1         : out std_logic_vector(WIDTH-1 downto 0);
DOUT0_ADDR    : in  std_logic_vector(3 downto 0);
DOUT1_ADDR    : in  std_logic_vector(3 downto 0)
        );
  end;
architecture RTL of REGS is
signal reg0  : std_logic_vector(WIDTH-1 downto 0);
signal reg1  : std_logic_vector(WIDTH-1 downto 0);
signal reg2  : std_logic_vector(WIDTH-1 downto 0);
signal reg3  : std_logic_vector(WIDTH-1 downto 0);
signal reg4  : std_logic_vector(WIDTH-1 downto 0);
signal reg5  : std_logic_vector(WIDTH-1 downto 0);
signal reg6  : std_logic_vector(WIDTH-1 downto 0);
signal reg7  : std_logic_vector(WIDTH-1 downto 0);
signal reg8  : std_logic_vector(WIDTH-1 downto 0);
signal reg9  : std_logic_vector(WIDTH-1 downto 0);
signal reg10 : std_logic_vector(WIDTH-1 downto 0);
signal reg11 : std_logic_vector(WIDTH-1 downto 0);
signal reg12 : std_logic_vector(WIDTH-1 downto 0);
signal reg13 : std_logic_vector(WIDTH-1 downto 0);
signal reg14 : std_logic_vector(WIDTH-1 downto 0);
signal reg15 : std_logic_vector(WIDTH-1 downto 0);
begin
data_in : process(CLK, DIN, DIN_ADDR, WEN)
begin
  if (CLK'EVENT and CLK = '0' and WEN = '1')  then
    case DIN_ADDR is
when "0000" => reg0  <= DIN;
when "0001" => reg1  <= DIN;
when "0010" => reg2  <= DIN;
when "0011" => reg3  <= DIN;
when "0100" => reg4  <= DIN;
when "0101" => reg5  <= DIN;
when "0110" => reg6  <= DIN;
when "0111" => reg7  <= DIN;
when "1000" => reg8  <= DIN;
when "1001" => reg9  <= DIN;
when "1010" => reg10 <= DIN;
when "1011" => reg11 <= DIN;
when "1100" => reg12 <= DIN;
when "1101" => reg13 <= DIN;
when "1110" => reg14 <= DIN;
when "1111" => reg15 <= DIN;
when others => null;
    end case;
  end if;
end process;
DOUT0 <= reg0  when  DOUT0_ADDR = "0000" else
reg1  when  DOUT0_ADDR = "0001" else
reg2  when  DOUT0_ADDR = "0010" else
reg3  when  DOUT0_ADDR = "0011" else
reg4  when  DOUT0_ADDR = "0100" else
reg5  when  DOUT0_ADDR = "0101" else
reg6  when  DOUT0_ADDR = "0110" else
reg7  when  DOUT0_ADDR = "0111" else
reg8  when  DOUT0_ADDR = "1000" else
reg9  when  DOUT0_ADDR = "1001" else
reg10 when  DOUT0_ADDR = "1010" else
reg11 when  DOUT0_ADDR = "1011" else
reg12 when  DOUT0_ADDR = "1100" else
reg13 when  DOUT0_ADDR = "1101" else
reg14 when  DOUT0_ADDR = "1110" else
reg15 ;
DOUT1 <= reg0  when  DOUT1_ADDR = "0000" else
reg1  when  DOUT1_ADDR = "0001" else
reg2  when  DOUT1_ADDR = "0010" else
reg3  when  DOUT1_ADDR = "0011" else
reg4  when  DOUT1_ADDR = "0100" else
reg5  when  DOUT1_ADDR = "0101" else
reg6  when  DOUT1_ADDR = "0110" else
reg7  when  DOUT1_ADDR = "0111" else
reg8  when  DOUT1_ADDR = "1000" else
reg9  when  DOUT1_ADDR = "1001" else
reg10 when  DOUT1_ADDR = "1010" else
reg11 when  DOUT1_ADDR = "1011" else
reg12 when  DOUT1_ADDR = "1100" else
reg13 when  DOUT1_ADDR = "1101" else
reg14 when  DOUT1_ADDR = "1110" else
reg15;
end RTL;