急求高手编程指教

893198256

library ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity div_out is
port( din,clk:in std_logic;
chk:in std_logic_vector(7 downto 0);
en,reset:in std_logic;
div_clkut std_logic_vector(11 downto 0);
smut std_logic_vector(3 downto 0);  --A或0
qut std_logic_vector(7 downto 0));
end div_out;
architecture behav of div_out is
signal temp:std_logic_vector(7 downto 0);
signal count:integer range 0 to 7 :=0;
signal num: std_logic;
signal y:std_logic_vector(7 downto 0);
signal D:std_logic_vector(7 downto 0);
SIGNAL c :INTEGER RANGE 0 TO 8;
  signal m:STD_LOGIC_VECTOR(11 DOWNTO 0);
begin
p1:process(clk)
begin
if(clk'event and clk='1')then
m<="000000000000";
if(m="110000110100")then
m<= (OTHERS =>'0');
num <=NOT num;
else
m<=m+1;
end if;
end if;
end process p1;
div_clk<=num;
p2:process(en,reset,clk,din)
begin
if reset='0'then
count<=0;
temp<="00000000";
q<="00000000";
else if(en='1')
then if(clk'event and clk='1')then
if(count=7)then
temp(count)<=din;
y(count)<=din;
q<=temp;
count<=count-1;
else if(count<7and count>0)then
temp(count)<=din;
y(count)<=din;
count<=count-1;
else
temp(0)<=din;
y(0)<=din;
count<=7;
end if;
end if;
end if;
end if;
end if;
end process p2;
p3:process(clk,reset)
begin
D<=chk;
    if reset='0' then
       c<=0;
    elsif clk'event and clk='1' then  --时钟到来时，判断并处理当前输入的位
        CASE c IS
WHEN 0 =>   IF DIN =D(7) THEN c<= 1 ;ELSE c<=0;END IF;
WHEN 1 =>   IF DIN =D(6) THEN c<= 2 ;ELSE c<=0;END IF;
WHEN 2 =>   IF DIN =D(5) THEN c<= 3 ;ELSE c<=0;END IF;
WHEN 3 =>   IF DIN =D(4) THEN c<= 4 ;ELSE c<=0;END IF;
WHEN 4 =>   IF DIN =D(3) THEN c<= 5 ;ELSE c<=0;END IF;
WHEN 5 =>   IF DIN =D(2) THEN c<= 6 ;ELSE c<=0;END IF;
WHEN 6 =>   IF DIN =D(1) THEN c<= 7 ;ELSE c<=0;END IF;
WHEN 7 =>   IF DIN =D(0) THEN c<= 8 ;ELSE c<=0;END IF;
WHEN OTHERS => c<=0;
END CASE;
END IF;
END PROCESS ;
PROCESS(c)
BEGIN
      IF c=8  THEN sm<= "1010";      
      ELSE          sm<= "0000";              
      END IF ;
END PROCESS;
END behav;
在这个程序中，我在编译时，发现那个H<=H+1,总是出现不能定义加法操作，这是咋回事呀？求高手指教。

remnant

vhdl中，不能出现 H <= H + 1这种写法，也就是自己驱动自己。
需要先定义一个variable， 然后variable = H; H = variable + 1(太久不用vhdl，具体语法不记得了，你自己修改到正确语法吧）

taluopai

这格式。。。建议楼主排一下版，没找到H <= H + 1

qingxuan1

好久没写  VHDL了

qlengyu

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

在程序开头把这几个数据包添加上试试