求助

tanchunhua

我是刚学习FPGA的菜鸟，现在弄一个简单的驱动数码管显示的程序，请教波形仿真怎么弄，用的是modelism仿真，
library ieee;
use ieee.std_logic_1164.all;
entity aa is
port (
       i3,i2,i1,i0:in std_logic;
     a,b,c,d,e,f,gut std_logic
     );
end aa;
architecture rtl of aa is
signal indata:std_logic_vector(3 downto 0);
signal outdata:std_logic_vector(6 downto 0);
begin
   process(indata)
      begin
     indata<=i3&i2&i1&i0;
    case indata is
       when"0000"=>outdata<="1111110";
      when"0001"=>outdata<="0110000";
      when"0010"=>outdata<="1101101";
      when"0011"=>outdata<="1111001";
      when"0100"=>outdata<="0110011";
      when"0101"=>outdata<="1011011";
      when"0110"=>outdata<="0011111";
      when"0111"=>outdata<="1110000";
      when"1000"=>outdata<="1111111";
      when"1001"=>outdata<="1111011";
      when others=>outdata<="0000000";
      end case;
      a<=outdata(0);
      b<=outdata(1);
      c<=outdata(2);
      d<=outdata(3);
      e<=outdata(4);
      f<=outdata(5);
      g<=outdata(6);
  end process;
  end;
代码是这样的，我自己写了个testbench文件
library ieee;
use ieee.std_logic_1164.all;
entity aa_tb is
end;
architecture behavior of aa_tb is
  component aa
    port (
         i3,i2,i1,i0:in std_logic;
       a,b,c,d,e,f,gut std_logic
       );
  end component;
signal i3: std_logic:='0';
signal i2: std_logic:='0';
signal i1: std_logic:='0';
signal i0: std_logic:='0';
signal a: std_logic;
signal b: std_logic;
signal c: std_logic;
signal d: std_logic;
signal e: std_logic;
signal f: std_logic;
signal g: std_logic;
begin
DUT:aa port map(i3=>i3,i2=>i2,i1=>i1,i0=>i0,a=>a,b=>b,c=>c,d=>d,e=>e,f=>f,g=>g);
  TB: process
  begin
    wait for 20ns;
    i3<='1';
    wait for 40ns;
       i2<='1';
       wait for 60ns;
          i2<='1';
          wait for 80ns;
             i1<='1';
            wait for 100ns;
    i0<='1';
    wait for 200ns;
    wait;
  end process;
end;
  仿真不出来，求助，谢谢啦！

shiyinjita

你用verilog写吧？
'timescale 1ns/1ns
module test_bench ;
reg .......
  wire .......
aa aa() ;
initial
begin
{i3,i2,i1,i0 } = 4'b0000 ;
#10
{i3,i2,i1,i0} = 4'b0001 ;(也可以采用task来写)
#10 $stop
end

endmodule