一个模块（RTL级）做成硬核的大体流程是什么？顶层如何调用硬核？

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一个模块做成硬核的大体流程是什么？顶层如何调用硬核？

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1. pin location finalized for this block
2. block level place&route, floorplan ,
3. timing driven flow till gds2 , postroute
4. extract interface model or extracted timing model  for tihs block
so top level can use ETM/ILM ,
5. block level output lef (abstract view) for top level ,

top level instanialize the block in verilog  via pin connections ,