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发表于 2010-7-12 08:54:43
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http://www.google.com.hk/search?sourceid=chrome&ie=UTF-8&q=PFD+PLL+theoryPhase Frequency Detectors (PFD)
The phase detector generates the error signal required in the feedback loop of the synthesizer. The majority of PLL ASICs use a circuit called a Phase Frequency Detector (PFD) similar to the one shown in Figure 6. Compared with mixers or XOR gates, which can only resolve phase differences in the +/- p range, the PFD can resolve phase differences in the +/- 2p range or more (typically “frequency difference” is used to describe a phase difference of more than 2p, hence the term “phase frequency detector.” This circuit shortens transient switching times and performs the function in a simple and elegant digital circuit.
The PFD compares the reference signal Fr with that of the divided down VCO signal (Fvco/N) and activates the charge pumps based on the difference in phase between these two signals. The operational characteristics of the phase detector circuitry can be broken down into three modes: frequency detect, phase detect, and phase locked mode. When the phase difference is greater than ±2p, the device is considered to be in frequency detect mode. In frequency detect mode the output of the charge pump will be a constant current (sink or source, depending on which signal is higher in frequency.)
The loop filter integrates this current and the result is a continuously hanging control voltage applied to the VCO. The PFD will continue to operate in this mode until the phase error between the two input signals drops below 2p. |
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