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# Archive C:\澳洲大学VHDL讲义1_9.rar
2008-08-17 22:20 1031680 493276 d41c9392 Topic_01_Integrated Circuit Design_08.ppt
2008-08-17 22:21 192512 44600 c9917663 Topic_02_VHDL_S1_08.ppt
2008-08-17 22:21 1067520 563761 0ed838fa Topic_03_data_types_08.ppt
2008-08-27 01:25 467968 200016 c789c9f6 Topic_04_behavioral_Synthesis_08.ppt
2008-08-27 01:25 215552 141216 54ebaee4 Topic_04_behavioral_Synthesis_part b -08.ppt
2008-08-27 01:26 227328 72296 1c565d50 Topic_05_DataFlow_08.ppt
2008-08-27 01:26 566784 442213 52af4205 Topic_05_Finite_State_Machines_part1_08.ppt
2008-08-27 01:26 513024 207933 31e7d801 Topic_06_Finite_State_Machines _part2_08.ppt
2008-08-27 01:27 284672 58162 a6464c26 Topic_07_design_partitioning_08.ppt
2008-08-27 01:27 211456 67998 0605148b Topic_07_design_partitioning_conf_08.ppt
2008-08-27 01:28 164352 87808 9982bff5 Topic_08_test_benches_08.ppt
2008-08-27 01:27 195072 124098 9617aad3 Topic_09_Static_Timing_Analysis_ClockV2_08.ppt
2008-10-28 17:59 1044480 608910 18ccfe06 Topic_10_Pipelining.ppt
# 6182400 3112287 13 |
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