补充一下:
我在网上查到对show ahead fifo的解释:
show ahead mode allowing the early reading of the next read address.
Show-ahead synchronous FIFO mode treats the rdreq signal as a read-acknowledge signal to minimize the FIFO's read latency. The FIFO outputs data when it is available; assertion of rdreq acknowledges the data and causes the FIFO to output the next data word if available.
是不是指当read_en有效时,数据线上对应的数据就是有效的数据。
不同于一般的memory,读使能有效后1~n个cycle之后才有有效数据。