LDO PSR的提升讨论

sunjimmy

2020_2020_A 5.6uA Wide Bandwidth, High Power Supply Rejection Linear Low-Dropout Regulator with 68dB of PSR Up to 2MHz

Abstract
High power supply rejection (PSR) with a wide rejection frequency band is becoming a critical requirement in linear low-dropout regulators (LDOs) used in complex systems-on-chip (SOCs). Typical LDOs achieve higher PSR within their loop-bandwidth; however, their supply rejection performance degrades with reduced loop-gain outside their loop-bandwidth. Typical LDOs with external filtering capacitors may also have spectral peaking in their PSR response, causing excess system-level supply noise. This work presents an LDO design approach, which achieves a PSR of higher than 68 dB up to 2 MHz frequency and over a wide range of loads up to 250 mA. The wide PSR bandwidth is achieved using a current-mode feedforward ripple canceller (CFFRC) amplifier which provides up to 25 dB of PSR improvement. The feedforward path gain is inherently matched to the forward gain of the LDO, not requiring calibration. The LDO has a fast load transient response with a recovery time of 6.1 \mu \text {s} and has a quiescent current of 5.6 \mu \text {A}. For a full load transition, the LDO achieves settling with overshoot and undershoot voltages below 27.6 and 36.36 mV, respectively. The LDO is designed and fabricated in a 180 nm bipolar/CMOS/DMOS (BCD) technology. The CFFRC amplifier helps to achieve low quiescent power due to its inherent current mode nature, eliminating the need for supply ripple summing amplifiers and adaptive biasing.

sunjimmy

2018_A 65-nm CMOS Low Dropout Regulator Featuring -60-dB PSRR Over 10-MHz Frequency Range_JSSC

sunjimmy

2013_A 25mA CMOS LDO with -85dB PSRR at 2.5MHz_ASSCC 2013

sunjimmy

2012_A 30-mA CMOS Low Dropout Regulator for WiMAX Analog Front Ends with 50 dB PSRR at 10 MHz

sunjimmy

2009_A 25mA 0.13um CMOS LDO Regulator with PSR Better Than -56dB up to 10MHz Using Feedforward Ripple-Cancellation Technique_ISSCC 2009

sunjimmy

native NMOS is free device in most CMOS process node. NMOS without channel implant is native NMOS.
Most foundry didn't provide this model because they didn't characterize it and made a spice model for it. You may ask your foundry for it in case they had it already, but didn't release to customers.

Without native NMOS, you may try the architecture in "2013_A 25mA CMOS LDO with -85dB PSRR at 2.5MHz_ASSCC 2013". It seems that this architecture can fulfill your requirement.