DC check_timing 报告 end_points are not constrained for maximum delay

keppel7000

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Nont constrained end points in either DC /PT will have only Ouput ports or Data pin of the Flip flip. So you dont need to check for the ports. Ports doesnt come with hirerachy (first two pins).

how to debug these points.

Check the registers. and check the clock is reaching. If clock is not reaching, then its unconstrained.
if clock is reaching need to check below points.
a. Is there any false path to these registers.
b.Is there any disabled timing , which is masking the timing checks.
c. you might have applied max_delay dealy and may be have syntax issues.

All above that, set *unconstrained* variable to true in PT and check report_timing -exceptions all command will give better idea, why this path is unconstrained.