HIGH-SPEED CMOS COMPARATOR

kevinwjs

1 Introduction 1
1.1 General information .........................................................................................1
1.2 Background ......................................................................................................2
1.2.1 A high-speed CMOS comparator with 8-bit resolution.............................................2
1.2.2 A 6-bit 1 GHz acquisition speed CMOS flash ADC with digital error correction.....3
1.2.3 A 0.35 9m CMOS comparator circuit for high-speed ADC applications .................5
1.2.4 Performance analysis of optimized CMOS comparator ...........................................6
1.3 Scope of the work ............................................................................................7
1.4 Outline .............................................................................................................7
2 Theory 9
2.1 Pre-amplifier ....................................................................................................9
1.2 Comparator offset.............................................................................................9
2.3 Kickback ........................................................................................................10
2.3.1 Sampling switches ..................................................................................................10
2.3.2 Isolation transistors .................................................................................................11
2.3.3 Pre-amplifier...........................................................................................................11
2.3.4 Neutralization technique .........................................................................................11
2.4 Parasitics ........................................................................................................11
2.5 Metastability ..................................................................................................12
3 Design details 15
3.1 CMOS latch circuit........................................................................................................15
3.1.1 Comparator Optimization .......................................................................................16
a) Transistors M1-M3 ...............................................................................................16
b) Transistors M4 & M5 ............................................................................................17
c) Transistors M6 & M7 ............................................................................................17
d) Transistors M8 & M9 ............................................................................................17
3.2 SR Latch circuit .............................................................................................17
3.3 Two phase operation ......................................................................................18
3.4 Gain and bandwidth of the comparator ...........................................................19
3.5 Comparator turn off technique.........................................................................19
3.6 Settling time of the comparator .......................................................................20
3.7 Kickback noise ...............................................................................................21
4 Simulation results and discussion 23
4.1 Final simulations ............................................................................................23
4.2 The performance and design parameters.........................................................25
4.3 Conclusion and discussion .............................................................................25