数字IC设计资料(IC前端|FPGA|ASIC) 今日: 8 |主题: 26357|排名: 4

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[资料] M3 M0交换学习资料	ASIC88TOM 2024-7-26	6954	fengsui 2024-10-10 05:35
[资料] signed 2's complement 和signed 1's complement 区别	浪海 2020-6-30	43588	catannie 2024-10-9 19:00
[原创] 112G ETHERNET PHY ...2 3	Beninggg 2024-3-4	216025	rchsc 2024-10-9 16:55
cadence版图设计教程和仿真教程 ...2 3 4 5 6..63	kongchau 2008-12-18	62979273	i0977454522 2024-10-9 16:32
[资料] Architecting High-Performance Embedded Systems @2021 ...2 3 4 5 6	2046 2022-10-26	528818	skahill 2024-10-9 14:20
[资料] 综合与时序分析的设计约束 Synopsys设计约束(SDC).pdf ...2	tengjiexx 2023-5-6	124639	PYGH 2024-10-8 19:34
[资料] 基于FPGA的软件无线电DDC设计 ...2 3 4 5 6..7	智慧棒 2012-1-27	6018622	rfyong 2024-10-8 17:27
[资料] 时序约束和时序分析，看这两本就足够了 ...2 3 4 5 6..22	gooseman 2018-10-8	21357876	clslhy 2024-10-8 16:47
FPGA在软件无线电中的应用	cooperation 2007-4-1	82159	zhangming325 2024-10-8 16:09
[求助] 求问！Synopsys Designware库中数据是从哪个流程优化来的？	Moumo 2024-3-1	2821	Patrick0809 2024-10-8 15:53
[求助] verdi创建的.v文件导入报错，求解	木石 2017-9-5	54632	Patrick0809 2024-10-8 15:48
[求助] [求助] synopsys的vcs安装有误——/bin/sh: 0: Illegal option -h	great_sun 2024-4-20	1621	Patrick0809 2024-10-8 14:50
[资料] 基于FPGA的软件无线电高级培训班的精品资料 ...2	智慧棒 2011-8-21	194551	zhangming325 2024-10-8 14:21
[资料] FPGA-Verilog学习之红外接收解码_红外接收源码	明德扬教育 2017-8-3	73012	keenboyee 2024-10-8 11:08
Xilinx的FPGA设计全流程：Modelsim－Synplify.Pro－ISE.rar ...2 3 4 5 6..31	chengzhenjun 2007-3-31	30440481	ic886 2024-10-7 22:38
[原创] synopsys的DMAC，需要自取 ...2	wangli_peking 2023-6-12	194128	clslhy 2024-10-7 22:00
[资料] JESD79-4B，欢迎下载！ ...2	litaoilet 2022-11-24	101650	clslhy 2024-10-7 21:59
[资料] low power design ...2 3 4 5	Avalon 2016-1-26	448872	clslhy 2024-10-7 21:55
[资料] synopsys designware ahci sata databook ...2	sunfire 2012-5-21	168161	clslhy 2024-10-7 21:18
[资料] onfi 5 协议	dreamfly123123 2024-3-28	91478	clslhy 2024-10-7 21:15
[资料] hdmi2.1协议 ...2 3	juhuapaul 2020-4-27	2611056	skahill 2024-10-7 19:54
[资料] 【第四版】Digital Video and Audio Broadcasting Technology ...2	lyoovue 2024-6-25	133207	clslhy 2024-10-7 14:12
[求助] 《数字滤波器的MATLAB与FPGA实现——Altera/Verilog版（第2版）》 ...2	xiewushuang 2021-7-15	192830	li_john 2024-10-7 11:28
[资料] Verilog设计教程-夏宇闻.pdf	tengjiexx 2023-5-6	82160	NANHU_BRUCE 2024-10-6 18:45
[资料] Designing with Xilinx FPGAs_ Using Vivado》 ...2 3 4 5 6	lanzhang 2021-1-2	5816678	tomedavid 2024-10-6 11:28
[资料] Advanced HDL Synthesis and SOC Prototyping ...2 3	xiaohaolaoda 2021-8-25	265371	zhb9103 2024-10-5 20:18
[资料] Computer Arithmetic--Algorithms and Hardware Designs--2nd Edition ...2	kl_upc 2024-5-24	164026	zhb9103 2024-10-5 20:17
[资料] Synopsys和Cadence最新软件网盘分享4(13年11月更新) ...2 3 4 5 6..10	504472832 2013-11-6	9844460	robinfit01 2024-10-5 18:41
Advanced Computer Architecture and.Parallel Processing.pdf ...2 3 4 5	ching 2009-3-12	469198	zhb9103 2024-10-5 12:37
AD1853(24bit 192kHz采样速率立体声多比特ΣΔ数模转换器)	caoshangfei 2008-3-8	62458	gubels 2024-10-3 23:20
[资料] verilog代码	齐天大胜 2024-6-5	61112	cikulangsat 2024-10-3 16:01
[原创] USB Sniffer 一个开源的USB协议analyzer	dodoee 2024-8-14	11585	cikulangsat 2024-10-3 15:54
[原创] VERISILICON_SMIC13_V1.0 ...2 3 4 5 6..8	amonghsh006 2011-7-22	7927699	igolaps 2024-10-2 21:35
Cadence SpectreRF PowerPoint file ...2 3 4	hi_china59 2009-9-7	319135	igolaps 2024-10-2 17:40
[原创] SMIC.18工艺库, 包括IO,STD,PLL等 ...2 3 4 5 6..10	xdpeter 2013-2-20	9046224	igolaps 2024-10-1 16:25

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数字IC设计资料(IC前端|FPGA|ASIC) 今日: 8 |主题: 26357|排名: 4

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