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发表于 2018-12-11 14:18:37
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本帖最后由 american007 于 2018-12-11 14:34 编辑
请教楼上,现在就弄了个最简单的文件led_test.v如下,换DEFAULT还是不行
led_test.v
`timescale 1ns / 1ps
module led_test (
sys_clk ,
rst_n,
led
);
input sys_clk;
input rst_n;
output [3:0] led;
reg [31:0] timer;
reg [3:0] led;
always @(posedge sys_clk or negedge rst_n)
begin
if (~rst_n)
timer <= 0;
else if (timer == 32'd199_999_999)
timer <= 0;
else
timer <= timer + 1'b1;
end
always @(posedge sys_clk or negedge rst_n)
begin
if (~rst_n)
led <= 4'b0000;
else if (timer == 32'd49_999_999)
led <= 4'b0001;
else if (timer == 32'd99_999_999)
led <= 4'b0010;
else if (timer == 32'd149_999_999)
led <= 4'b0100;
else if (timer == 32'd199_999_999)
led <= 4'b1000;
end
endmodule
先用命令 vlogan -full64 -work DEFAULT led_test.v ,
[lq@simuhost simu_test3]$ vlogan -full64 -work DEFAULT led_test.v
Warning-[MXIR-W] VCS-MX build is required
Please make sure that vlogan is from the intended build.
Chronologic VCS (TM)
Version L-2016.06_Full64 -- Wed Dec 12 14:40:33 2018
Copyright (c) 1991-2016 by Synopsys Inc.
ALL RIGHTS RESERVED
This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.
Parsing design file 'led_test.v'
CPU time: .052 seconds to compile
上面有个 报警 ?
得到下图
得到上面内容,对吗 ?是不是不太对,work目录里就一个AN.DB文件夹,AN.DB里就是 上图那一堆,
里面 也没有个啥叫led_test的文件,然后vcs -full64 DEFAULT.led_test,得到错误提示
[lq@simuhost simu_test3]$ vcs -full64 DEFAULT.led_test
Chronologic VCS (TM)
Version L-2016.06_Full64 -- Wed Dec 12 14:25:12 2018
Copyright (c) 1991-2016 by Synopsys Inc.
ALL RIGHTS RESERVED
This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.
Error-[SFCOR] Source file cannot be opened
Source file "DEFAULT.led_test" cannot be opened for reading due to 'No such
file or directory'.
Please fix above issue and compile again.
1 error
CPU time: .087 seconds to compile |
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