Unless declared in a dynamic context—within a class or an automatic task—all variables in SystemVerilog are static by default. Static variables are not really an unspecified behavior in System-Verilog but can be a source of unexpected behavior. A single copy exists for a static variable. It is created and initialized at the beginning of the simulation and is reused by all threads referencing that variable. A variable in a dynamic scope or explicitly declared as automatic is created and initialized every time a thread enters the scope in which the dynamic variable is declared.