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[求助] systemverilog 同一个function被多个地方同时调用

发表于 2016-10-24 20:19:40 | 显示全部楼层 |阅读模式


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发表于 2016-10-25 08:56:06 | 显示全部楼层
回复 1# cy_00521

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发表于 2016-10-30 22:06:54 | 显示全部楼层
回复 2# chensong0007

Variables are static by default.

Unless declared in a dynamic context—within a class or an automatic task—all variables in SystemVerilog are static by default. Static variables are not really an unspecified behavior in System-Verilog but can be a source of unexpected behavior. A single copy exists for a static variable. It is created and initialized at the beginning of the simulation and is reused by all threads referencing that variable. A variable in a dynamic scope or explicitly declared as automatic is created and initialized every time a thread enters the scope in which the dynamic variable is declared.
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