Clock need accuracy delay time of cell and wire load. In Synthesis procedure, it only transfer the RTL Verilog to gate level Verilog. The wile load mode and standard cell delay timing is still not accuracy enough for real clock skew calculation.
So, normally will put the clock synthesis into Auto Place & Route procedure to handle. If it's only a simply local small area clock. U can also fix the se ...
Clock need accuracy delay time of cell and wire load. In Synthesis procedure, it only transfer the RTL Verilog to gate level Verilog. The wile load mode and standard cell delay timing is still not accuracy enough for real clock skew calculation.
So, normally will put the clock synthesis into Auto Place & Route procedure to handle. If it's only a simply local small area clock. U can also fix the setup/hold time in synthesis because it's low risk.
Agree "jinwei91".
The RC calculated from WLM in DC is so different than real RC, so synthesizing clock is no sense wasting time.
If we use this synthesized data to optimize clock tree after placement, it may increase the complexity of clock trees, chip size and power consumption.
The main purpose of synthesis is to do logic mapping and optimization, under assumption of ideal clock network. Since the floorplan and all the other physical info is not compulsory in synthesis stage, and hence the instances are not placed, it is better not to touch the clock network.
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发表于 2014-5-8 10:12:46
发表于 2014-5-8 10:12:47
因为DC算不准时钟树的延时。不知道reg的具体位置，时钟具体用哪些层连线。
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