请高人指点 Verilog 数字时钟的键盘调时

yzh0122jy · 发表于 2011-5-12 20:19:22

马上注册，结交更多好友，享用更多功能，让你轻松玩转社区。

您需要登录才可以下载或查看，没有账号？注册

x

在实现键盘调时是按一下change键会一下加了很多数不知道具体是什么原因以为是需要键盘防抖可是加上了键盘到不好使了怎么按都调不了了帮忙指点一下啊急死了这个用的时钟clk是100MHZ的

module caclock(clk, key_in, key_out, cpld_e, counter);
input clk;
input [5:0] key_in;
output [3:0] key_out;
output [1:0] cpld_e;
output [15:0] counter;
//状态器状态值
reg[15:0] counter;
reg[3:0] key_out;
reg[2:0] state =3'b000;
reg[9:0] key_value;
reg ND = 0;
reg clk_20ms_r=0;
reg[6:0] cnt_f=7'b0;
reg[31:0] cnt_s=32'd0;
reg[7:0] sec=8'h0;
reg[7:0] min=8'h0;
reg[7:0] hour=8'h0;
reg[7:0] day=8'h1;
reg[7:0] mon=8'h5;
reg[7:0] year=8'h11;
reg[3:0] week=4'h7;//开机显示日历为11年05月01日,星期七
reg[0:0] clk_f=1'b1;
reg[0:0] clk_s=1'b1;
reg[0:0] clk_m=1'b1;
reg[0:0] clk_h=1'b1;
reg[0:0] clk_d=1'b1;
reg[0:0] clk_mon=1'b1;
reg[0:0] clk_y=1'b1;
reg[7:0] inta=8'd0;
reg flag=0;
reg[1:0] e=2'd0;
reg[1:0] t=2'd0;
reg turn,change,enter;
reg chg_y,chg_mon,chg_d,chg_w,chg_h,chg_m;
wire yclk,monclk,dclk,wclk,hclk,mclk;
assign cpld_e=2'b01;
always@(posedge clk)
begin
if(cnt_f==7'b1000000)
begin
clk_f<=~clk_f;
cnt_f<=0;
end
else
cnt_f<=cnt_f+1;
end
always@(posedge clk) //得到周期为1s的脉冲信号
begin
if(cnt_s==32'd50000000)
begin
clk_s<=~clk_s;
cnt_s<=0;
end
else
cnt_s<=cnt_s+1;
end
//以下是通过按键实现调时功能
always @(posedge clk) //检查是哪个按键按下
begin
case (state)
0: begin
key_out[3:0]=4'b0000;
ND=0;
if(key_in !=6'b111111)
begin
state=1;
key_out[3:0]=4'b1110;
end
else
state=0;
end
1: begin
if(key_in !=6'b111111)
begin
state=5;
end
else
begin
state=2;
key_out[3:0]=4'b1101;
end
end
2: begin
if(key_in !=6'b111111)
begin
state=5;
end
else
begin
state=3;
key_out[3:0]=4'b1011;
end
end
3: begin
if(key_in !=6'b111111)
begin
state=5;
end
else
begin
state=4;
key_out[3:0]=4'b0111;
end
end
4: begin
if(key_in !=6'b111111)
begin
state=5;
end
else
state=0;
end
5: begin
if(clk_20ms_r == 2000000)
begin
key_value[9:0]={key_in,key_out};
ND=1;
state=0;
clk_20ms_r <= 20'b0;
end
else
clk_20ms_r <= clk_20ms_r+1'b1;
end
endcase
end
always @(clk_f or key_in or key_out)
begin
if(ND==1)
begin
case(key_value)
10'b1111101011:turn<=0; //按键“turn”（即按键0）被按下时
10'b1101111110:change<=0; //按键“change”（即按键+）被按下时
10'b0111111110:enter<=0; //按键“切换”（即按键enter）被按下时
default:{turn,change,enter}<=3'b111;//将三个按键置1，即按键没被按下
endcase
end
else
{turn,change,enter}<=3'b111;//将三个按键置1，即按键没被按下
end
always@(negedge enter) //enter信号控制系统在三种功能间的转换,即正常显示、调整日历、调整时钟
begin
if(e==2)
e<=0;
else
e<=e+1;
end
always@(negedge turn) //turn信号控制显示调整当前调整参数右侧的参数
begin
if(t==3)
t<=0;
else
t<=t+1;
end
always@(negedge change)
begin
case(e)
2:begin //e=2是调整日历
if(t==0)
begin
chg_y<=!change;
end
else if(t==1)
begin
chg_mon<=!change;
end
else if(t==2)
begin
chg_d<=!change;
end
else
begin
chg_w<=!change;
end
{chg_h,chg_m}<=2'b00;
end
1:begin //e=1是调整时钟
if(t==0)
begin
chg_h<=!change;
end
else if(t==1)
begin
chg_m<=!change;
end
else if(t==2)
begin
chg_h<=!change;
end
else
begin
chg_m<=!change;
end
{chg_y,chg_mon,chg_d,chg_w}<=4'b0000;
end
default:{chg_y,chg_mon,chg_d,chg_w,chg_h,chg_m}<=0;
endcase
end
//以下是计时功能
always@(posedge clk_s) //秒计数的变化，得到周期为1秒的脉冲信号clk_m
begin
if(!(sec^8'h59)|(!turn)&(!e))
begin
sec<=0;
if(!((!turn)&(!e)))
clk_m<=1;
end //按住“turn”按键一段时间，可使秒信号清零，该功能用于手动精确调时
else
begin
if(sec[3:0]==4'b1001)
begin
sec[3:0]<=4'b0000;
sec[7:4]<=sec[7:4]+1;
end
else
begin
sec[3:0]<=sec[3:0]+1;
clk_m<=0;
end
end
end
always@(posedge mclk) //分计数的变化，得到周期为1分钟的脉冲信号clk_h
begin
if(min==8'h59)
begin
min<=0;
clk_h<=1;
end
else
begin
if(min[3:0]==4'b1001)
begin
min[3:0]<=4'b0000;
min[7:4]<=min[7:4]+1;
end
else
begin
min[3:0]<=min[3:0]+1;
clk_h<=0;
end
end
end
always@(posedge hclk) //时计数的变化，得到周期为一天的脉冲信号clk_d
begin
if(hour==8'h23)
begin
hour<=0;
clk_d<=1;
end
else
begin
if(hour[3:0]==4'b1001)
begin
hour[3:0]<=4'b0000;
hour[7:4]<=hour[7:4]+1;
end
else
begin
hour[3:0]<=hour[3:0]+1;
clk_d<=0;
end
end
end
always@(posedge dclk) //天计数的变化，得到周期为月的脉冲信号clk_mon
begin
if(((mon<=4'b1000)&&(mon%2==1))||((mon>=4'b1000)&&(mon%2==0))) //当月份是1，3，5，7，8，10，12时制定clk_mon
begin
if(day==8'h31)
begin
day<=8'h01;
clk_mon<=1;
end
else
begin
if(day[3:0]==4'b1001)
begin
day[3:0]<=4'b0000;
day[7:4]<=day[7:4]+1;
end
else
begin
day[3:0]<=day[3:0]+1;
clk_mon<=0;
end
end
end
else if(mon==2) //当月份是2月时，制定脉冲信号clk_mon
begin
if(year%4==0) //年份是闰年时
begin
if(day==8'h29)
begin
day<=8'h01;
clk_mon<=1;
end
else
begin
if(day[3:0]==4'b1001)
begin
day[3:0]<=4'b0000;
day[7:4]<=day[7:4]+1;
end
else
begin
day[3:0]<=day[3:0]+1;
clk_mon<=0;
end
end
end
else //年份是平年时
begin
if(day==8'h28)
begin
day<=8'h01;
clk_mon<=1;
end
else
begin
if(day[3:0]==4'b1001)
begin
day[3:0]<=4'b0000;
day[7:4]<=day[7:4]+1;
end
else
begin
day[3:0]<=day[3:0]+1;
clk_mon<=0;
end
end
end
end
else //当月份是4，6，9，11时，制定脉冲信号clk_mon
begin
if(day==8'h30)
begin
day<=8'h01;
clk_mon<=1;
end
else
begin
if(day[3:0]==4'b1001)
begin
day[3:0]<=4'b0000;
day[7:4]<=day[7:4]+1;
end
else
begin
day[3:0]<=day[3:0]+1;
clk_mon<=0;
end
end
end
end
always@(posedge monclk) //月计数的变化，得到周期为年的脉冲信号clk_y
begin
if(mon==8'h12)
begin
mon<=8'h01;
clk_y<=1;
end
else
begin
if(mon[3:0]==4'b1001)
begin
mon[3:0]<=4'b0000;
mon[7:4]<=mon[7:4]+1;
end
else
begin
mon[3:0]<=mon[3:0]+1;
clk_y<=0;
end
end
end
always@(posedge yclk) //年计数的变化，只显示2000—2099年之间
begin
if(year==8'h99)
year<=0;
else
begin
if(year[3:0]==4'b1001)
begin
year[3:0]<=4'b0000;
year[7:4]<=year[7:4]+1;
end
else
year[3:0]<=year[3:0]+1;
end
end
always@(posedge wclk) //周计数的变化
begin
if(week==4'h7)
week<=4'h01;
else
week<=week+1;
end
assign yclk=clk_y||chg_y;
assign monclk=clk_mon||chg_mon;
assign dclk=clk_d||chg_d;
assign wclk=clk_d||chg_w;
assign hclk=clk_h||chg_h;
assign mclk=clk_m||chg_m;
always@(posedge clk_m)
flag<=~flag;
always@(posedge clk_f) //控制动态显示各位
begin
if(flag==0)
begin
if(inta==hour[7:4]+50)
inta=sec[3:0];
else if(inta==sec[3:0])
inta=sec[7:4]+10;
else if(inta==sec[7:4]+10)
inta=8'd16;
else if(inta==8'd16)
inta=min[3:0]+20;
else if(inta==min[3:0]+20)
inta=min[7:4]+30;
else if(inta==min[7:4]+30)
inta=8'd36;
else if(inta==8'd36)
inta=hour[3:0]+40;
else
inta=hour[7:4]+50;
case(inta)
0:counter<=16'h7F3F;
1:counter<=16'h7F06;
2:counter<=16'h7F5B;
3:counter<=16'h7F4F;
4:counter<=16'h7F66;
5:counter<=16'h7F6D;
6:counter<=16'h7F7D;
7:counter<=16'h7F07;
8:counter<=16'h7F7F;
9:counter<=16'h7F6F;
10:counter<=16'hBF3F;
11:counter<=16'hBF06;
12:counter<=16'hBF5B;
13:counter<=16'hBF4F;
14:counter<=16'hBF66;
15:counter<=16'hBF6D;
16:counter<=16'hDF40;
20:counter<=16'hEF3F;
21:counter<=16'hEF06;
22:counter<=16'hEF5B;
23:counter<=16'hEF4F;
24:counter<=16'hEF66;
25:counter<=16'hEF6D;
26:counter<=16'hEF7D;
27:counter<=16'hEF07;
28:counter<=16'hEF7F;
29:counter<=16'hEF6F;
30:counter<=16'hF73F;
31:counter<=16'hF706;
32:counter<=16'hF75B;
33:counter<=16'hF74F;
34:counter<=16'hF766;
35:counter<=16'hF76D;
36:counter<=16'hFB40;
40:counter<=16'hFD3F;
41:counter<=16'hFD06;
42:counter<=16'hFD5B;
43:counter<=16'hFD4F;
44:counter<=16'hFD66;
45:counter<=16'hFD6D;
46:counter<=16'hFD7D;
47:counter<=16'hFD07;
48:counter<=16'hFD7F;
49:counter<=16'hFD6F;
50:counter<=16'hFE3F;
51:counter<=16'hFE06;
52:counter<=16'hFE5B;
default:counter<=16'hFE7F;
endcase
end
else
begin
if(inta==year[7:4]+60)
inta=week;
else if(inta==week)
inta=8'd8;
else if(inta==8'd8)
inta=day[3:0]+10;
else if(inta==day[3:0]+10)
inta=day[7:4]+20;
else if(inta==day[7:4]+20)
inta=mon[3:0]+30;
else if(inta==mon[3:0]+30)
inta=mon[7:4]+40;
else if(inta==mon[7:4]+40)
inta=year[3:0]+50;
else
inta=year[7:4]+60;
case(inta)
0:counter<=16'h7F3F;
1:counter<=16'h7F06;
2:counter<=16'h7F5B;
3:counter<=16'h7F4F;
4:counter<=16'h7F66;
5:counter<=16'h7F6D;
6:counter<=16'h7F7D;
7:counter<=16'h7F07;
8:counter<=16'hBF40;
10:counter<=16'hDF3F;
11:counter<=16'hDF06;
12:counter<=16'hDF5B;
13:counter<=16'hDF4F;
14:counter<=16'hDF66;
15:counter<=16'hDF6D;
16:counter<=16'hDF7D;
17:counter<=16'hDF07;
18:counter<=16'hDF7F;
19:counter<=16'hDF6F;
20:counter<=16'hEF3F;
21:counter<=16'hEF06;
22:counter<=16'hEF5B;
23:counter<=16'hEF4F;
24:counter<=16'hEF66;
25:counter<=16'hEF6D;
26:counter<=16'hEF7D;
27:counter<=16'hEF07;
28:counter<=16'hEF7F;
29:counter<=16'hEF6F;
30:counter<=16'hF7BF;
31:counter<=16'hF786;
32:counter<=16'hF7DB;
33:counter<=16'hF7CF;
34:counter<=16'hF7E6;
35:counter<=16'hF7ED;
36:counter<=16'hF7FD;
37:counter<=16'hF787;
38:counter<=16'hF7FF;
39:counter<=16'hF7EF;
40:counter<=16'hFB3F;
41:counter<=16'hFB06;
42:counter<=16'hFB5B;
43:counter<=16'hFB4F;
50:counter<=16'hFDBF;
51:counter<=16'hFD86;
52:counter<=16'hFDDB;
53:counter<=16'hFDCF;
54:counter<=16'hFDE6;
55:counter<=16'hFDED;
56:counter<=16'hFDFD;
57:counter<=16'hFD87;
58:counter<=16'hFDFF;
59:counter<=16'hFDEF;
60:counter<=16'hFE3F;
61:counter<=16'hFE06;
62:counter<=16'hFE5B;
63:counter<=16'hFE4F;
64:counter<=16'hFE66;
65:counter<=16'hFE6D;
66:counter<=16'hFE7D;
67:counter<=16'hFE07;
68:counter<=16'hFE7F;
69:counter<=16'hFE6F;
default:counter<=16'h7F7F;
endcase
end
end
endmodule

复制代码

xinchen · 发表于 2011-5-13 11:27:32

先说一下我是菜鸟！没有看你的程序从你描述的情况来看，觉得是检测过快！你可以尝试检测按键放开以后再执行下面的任务！（这样做按一次建，不管按多长都只能加一）如果想实现能自动连续加可以在设置一个定时器，只有在按键没有松开的情况下定时满了自动加一。

silencex8 · 发表于 2011-5-14 18:38:16

不知道你是使用边沿，还是使用电平；最好使用边沿触发，同时防抖功能必须要的

[解决] 请高人指点 Verilog 数字时钟的键盘调时

马上注册，结交更多好友，享用更多功能，让你轻松玩转社区。

相关帖子

站长推荐 /3