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楼主: jerome555

[资料] SV(systemverilog)验证资料合集

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发表于 2011-6-11 13:36:20 | 显示全部楼层
Book:
SystemVerilog For Design
- Second Edition
- A Guide to Using SystemVerilog for Hardware Design and Modeling
- Year 2006
- 437 Pages
- Clean & Clear
发表于 2011-6-11 13:44:51 | 显示全部楼层
Verilog Digital System Design
- RT Level Synthesis, Testbench and Verification
- Second Edition
- Year 2006
- 402 Pages
- Clean & Clear
发表于 2011-6-11 13:47:29 | 显示全部楼层
Hardware Verification with SystemVerilog
- An Object-Oriented Framework
- Year 2007
- 332 Pages
- Clean & Clear
发表于 2011-6-11 13:52:01 | 显示全部楼层
HARDWARE VERIFICATION WITH C++
- A Practitioner’s Handbook
- Year 2006
- Page#:351
- Clean & clear
发表于 2011-6-11 13:54:26 | 显示全部楼层
Writing Testbenches Using SystemVerilog
- Year 2006
- Page#: 432
- Clean & Clear
发表于 2011-6-11 13:57:54 | 显示全部楼层
Verification methodology manual for SystemVerilog / by Janick Bergeron
- Year 2006
- Page#: 514
- Clean & Clear
发表于 2011-6-11 16:08:23 | 显示全部楼层
感谢楼主分享!!
发表于 2011-6-12 02:02:10 | 显示全部楼层
Digital System Design with SystemVerilog (draft)
- Year 2009
- Page#: 370
- W/O Cover Page
- Clear & Clean
发表于 2011-6-12 02:07:11 | 显示全部楼层
SystemVerilog for Verification:
- A Guide to Learning the Testbench Language Features
- Year 2006
- Page#:326
- W/O Cover Page
- Clean & Clear Version
发表于 2011-6-12 10:35:10 | 显示全部楼层
thanks for sharing
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