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本帖最后由 du_du404 于 2010-2-23 14:08 编辑
Digital IC Design and Verification
天津滨海集成电路设计服务中心将于2010年3月10日-11日举办Cadence公司设计定制课程“Digital IC Design and Verification”培训，以帮助IC工程师进一步全面系统地理解IC设计概念与方法和EDA工具的应用。培训将采用Cadence公司相关领域的培训教材，并由Cadence公司资深工程师主讲，培训方式以讲课和实验穿插进行。
Overview
This course covers 2 part of digital IC: Design and Verification.
The first part of this course is an introduction of digital IC design. It gives guidelines on how to set up good coding style for RTL design and how to write RTL for design for different level,from module level to SoC level.
The second part of this course is an introduction to the Incisive Plan-to-Closure Methodology (IPCM). IPCM defines how to perform a verificaiton process by going through plan, execute, measure and react process. It also introduces how to perform the process automatically.This 2 day course shows you how to write hdl code from module to SoC level design. It also provides guidance and practice to perform a coverage-driven-verification process automatically.
Objectives
In this course, you will:
● Learn how to set up coding style for RTL.
● Apply the coding style to module-level and SoC-level design
● Learn how to check coding style
● Learn a typical verification flow of from plan to closure
● Learn to implemente the verification process automatically
Course Outline
Day 1
● Module Level RTL design
● RTL Coding Style and rule check
● System-On-a-Chip Design
Day 2
● Verification Methodology
● Verification Plan
● Verification Execute
● Verification Measure
● Verification React
● Verification Process Management
Audience Profile
Design Engineers & Verification Engineers
At least one of the SystemC, VHDL, and verilog languages SystemVerilog Language and Application
Basic digital IC design, simulation, verification knowledge
Synopsys Tools Used
ncisive® DesignTeam Simulator
培训日期：2010年3月10日-2010年3月11日(食宿自理)
上课时间：上午9：30-11：30 下午1：00-4：30
名额限制：16人
地点：天津开发区第四大街80号天大科技园A1座2楼
联系人：赵先生
电话：66211352
传真：（+8622）66211339
E-mail：zhaozh@bicds.org | 
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发表于 2010-2-10 09:24:02
楼主
自己顶了！