A Top-Down Verilog-A Design on the Digital Phase-Locked Loop

小朱仔 · 发表于 2009-7-19 00:38:46

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A Top-Down verilog-A Design on the Digital Phase-Locked Loop

Chapter 1. Introduction
Chapter 2. Matlab System-Level Design and Simulation
Chapter 3. Verilog-A System-Level Design and Simulation
Chapter 4. Test Bench Study
Chapter 5. Entire DPLL Design and Simulation
Chapter 6. Conclusion
References

etc...

lelen · 发表于 2009-7-19 04:08:40

給樓主推一下~~~

生如夏花 · 发表于 2009-7-19 10:32:20

怎么下的人不多呢

wafergao · 发表于 2009-7-19 22:57:19

This is the document i want, 3ks!

jasonyschen · 发表于 2009-7-31 11:08:24

thanks very much

hedejun · 发表于 2009-8-11 13:59:12

thanks it is so great

plmhinc8010 · 发表于 2009-8-14 13:16:33

www.eece.maine.edu/vlsi/DPLL2003/Devon_Sanjeev.pdf

mihayilov · 发表于 2009-8-20 17:57:37

非常不错

rx1005 · 发表于 2009-8-20 19:05:10

mingho · 发表于 2009-9-6 01:35:38

thanks

A Top-Down Verilog-A Design on the Digital Phase-Locked Loop

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