回复 2# wide_road
不好意思,看的不是很明白。可以舉個例子嗎?假設我的toplevel是這個:
`timescale 1ns/10ps
module c103 ( N1, N2, N3, N4, N5, N6, N11 );
input N1, N2, N3, N4, N5, N6;
output N11;
wire n3, n4;
OA22X1_RVT U4 ( .A1(n3), .A2(N3), .A3(n4), .A4(N6), .Y(N11) );
AND2X1_RVT U5 ( .A1(N5), .A2(N4), .Y(n4) );
AND2X1_RVT U6 ( .A1(N2), .A2(N1), .Y(n3) );
endmodule
testbench是這個:
`include "saed32nm.v"
`timescale 1ns/10ps
module c103_tb();
reg N1, N2, N3, N4, N5, N6;
wire N11;
integer statusI,in, fileid;
c103 a ( N1, N2, N3, N4, N5, N6, N11 );
initial
$vcdpluson;//Record all signal value changes;
initial begin
in = $fopen("data6.txt","r");
fileid = $fopen("c103.txt","w");
repeat (100) begin
#5 statusI = $fscanf(in,"%h %h\n %h\n %h\n %h\n %h\n",N1, N2, N3, N4, N5, N6);
$display("|n3|n4|\n");
$monitor ("%t ",$time, c103.n3, c103.n4);
$strobe ("%t ",$time, c103.n3, c103.n4);
// $fwrite(fileid, "%t ",$time, N1, N2, N3, N4, N5, N6, "\t", N11,"\n" c103.n3, c103.n4);
end
$fclose(in);
$fclose(fileid);
#300 $finish;
end
endmodule
我想觀測node n3和n4.
目前我用的指令是:vcs c103_gate.v c103_benchmark.v -sverilog -debug_all +vcd+vcdpluson
請問應該怎麼改呢?
謝謝。 |